ISL267817
5
FN7877.2
April 19, 2012
REFERENCE INPUT
VREF
VREF Input Range
0.1
2.5
V
VREFLEAK Current Drain
-100
4
100
A
fSAMPLE = 12.5kHz
-20
0.23
20
A
CS/SHDN = +VCC
-3
0.01
3
A
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH
Input High Voltage
3
+VCC + 0.3
V
VIL
Input Low Voltage
-0.3
0.8
V
VOH
Output High Voltage
IOH = –250A
3.5
V
VOL
Output Low Voltage
IOL = 250A
0.4
V
Output Coding
Two’s Complement
ILEAK
Input Leakage Current
-1
1
A
CIN
Input Capacitance
10
pF
IOZ
Floating-State Output Current
-1
1
A
COUT
Floating-State Output Capacitance
5
pF
POWER REQUIREMENTS
VCC
Supply Voltage Range
4.75
5.25
V
ICC
Supply Current
430
800
A
fSAMPLE = 12.5kHz (Notes 8, 9) 38
A
fSAMPLE = 12.5kHz (Note 9) 223
A
Power Down Current
CS/SHDN = +VCC, fSAMPLE = 0Hz
0.5
3
A
TEMPERATURE RANGE
Specified Performance
-40
+85
°C
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
8. fDCLOCK = 3.2MHz, CS/SHDN = +VCC for 241 clock cycles out of every 256.
Electrical Specifications +VCC = +5V, fDCLOCK =3.2MHz, fS = 200kSPS, VREF = 2.5V; VCM = VREF, Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6) TYP
MAX
(Note 6)
UNITS
Timing Specifications Limits established by characterization and are not production tested. +VCC = 5V, fDCLOCK =3.2MHz, fS = 200kSPS,
VREF =2.5V; VCM = VREF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
tSMPL
Analog Input Sample Time
1.5
2.0
Clk Cycles
tCONV
Conversion Time
12
Clk Cycles
fCYC
Throughput Rate
200
kHz
tCSD
CS/SHDN Falling Edge to DCLOCK Low
0
ns
tSUCS
CS/SHDN Falling Edge to DCLOCK Rising Edge
30
ns
thDO
DCLOCK Falling Edge to Current DOUT Not Valid
15
ns