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參數(shù)資料
| 型號： | ISL28110FBZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/23頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP JFET 12.5MHZ LN 8SOIC |
| 產(chǎn)品培訓(xùn)模塊： | Patient Monitoring and Diagnostic Equipment Solutions Solutions for Test and Measurement Equipment Solutions for Industrial Control Applications |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | J-FET |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 20 V/µs |
| 增益帶寬積： | 12.5MHz |
| 電流 - 輸入偏壓： | 2pA |
| 電壓 - 輸入偏移： | 300µV |
| 電流 - 電源： | 2.55mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 9 V ~ 40 V，±4.5 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL28110FBZ-T7ADKR |
ISL28110, ISL28210
14
FN6639.3
November 29, 2012
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5 MHz
precision JFET input op amps. These devices are fabricated in the
PR40 Advanced Silicon-on-Insulator (SOI) bipolar-JFET process to
ensure latch-free operation. The precision JFET input stage
provides low input offset voltage (300V max @ +25°C), low
input voltage noise (6nV/
√Hz), and input current noise that is
very low with virtually no 1/f component. A high current
complementary NPN/PNP emitter-follower output stage provides
high slew rate and maintains excellent THD+N performance into
heavy loads (0.0003% @ 10VP-P @ 1kHz into 600Ω).
Operating Voltage Range
The devices are designed to operate over the 9V (±4.5V) to 40V
(±20V) range and are fully characterized at 10V (±5V) and 30V
(±15V). The JFET input stage maintains high impedance over a
maximum input differential voltage range of ±33V. Internal ESD
protection diodes clamp the non-inverting and inverting inputs to
one diode drop above and below the V+ and V- the power supply
rails (“Pin Descriptions” on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V reverse
breakdown voltage which enables the device to function reliably in
large signal pulse applications without the need for anti-parallel
clamp diodes required on MOSFET and most bipolar input stage
op amps. No special input signal restrictions are needed for
power supply operation up to ±15V, and input signal distortion
caused by nonlinear clamps under high slew rate conditions are
avoided. For power supply operation greater than ±16V (>32V),
the internal ESD clamp diodes alone cannot clamp the maximum
input differential signal to the power supply rails without the risk
of exceeding the 33V breakdown of the JFET gate. Under these
conditions, differential input voltage limiting is necessary to
prevent damage to the JFET input stage.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails, current
limiting resistors may be needed at each input terminal (see
ESD diodes to 20mA.
FIGURE 39. LARGE SIGNAL 10V STEP RESPONSE AV = -1
FIGURE 40. LARGE SIGNAL 10V STEP RESPONSE AV = +10
FIGURE 41. SETTLING TIME (tS) vs CLOSED LOOP GAIN
FIGURE 42. ZOUT vs FREQUENCY
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, T = +25°C, unless otherwise specified. (Continued)
-6
-4
-2
0
2
4
6
01
23
45
67
8
9
10
V
O
U
T
(V
)
TIME (s)
VS = ±15V
AV = -1
RL = 2k
CL = 4pF
VS = ±15V
AV = +10
RL = 2k
CL = 4pF
-6
-4
-2
0
2
4
6
012
34
56
78
9
10
V
O
U
T
(V
)
TIME (s)
1
10
100
0.1
1
10
100
CLOSED LOOP GAIN (V/V)
SETTL
ING
TI
ME
(s
)
VS = ±15V
0.01%
0.1%
VOUT = 10VP-P
RL = 2k
0.01
0.1
1
10
100
1000
10
100
1k
10k
100k
1M
10M
100M
Z
OU
T
(
)
FREQUENCY (Hz)
VS = ±15V
G = 1
G = 10
G = 100
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