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ISL28110, ISL28210
15
FN6639.3
November 29, 2012
JFET Input Stage Performance
The ISL28110, ISL28210 JFET input stage has the linear gain
characteristics of the MOSFET but can operate at high frequency
with much lower noise. The reversed-biased gate PN gate junction
has significantly lower gate capacitance than the MOSFET,
enabling input slew rates that rival op amps using bipolar input
stages. The added advantage for high impedance, precision
amplifiers is the lack of a significant 1/f component of current
noise (Figures 15, 16) as there is virtually no gate current.
The input stage JFETs are bootstrapped to maintain a constant
JFET drain to source voltage which keeps the JFET gate currents
and input stage frequency response nearly constant over the
common mode input range of the device. These enhancements
provide excellent CMRR, AC performance and very low input
distortion over a wide temperature range. The common mode input
performance for offset voltage and bias current is shown in
Figure 44. Note that the input bias current remains low even after
the maximum input stage common mode voltage is exceeded (as
indicated by the abrupt change in input offset voltage).
Output Drive Capability
The complementary bipolar emitter follower output stage features
low output impedance (Figure 42) and is capable of substantial
current drive over the full temperature range (Figures 29, 30) while
driving the output voltage close to the supply rails. The output
current is internally limited to approximately 卤50mA at +25掳C.
The amplifiers can withstand a short circuit to either rail as long as
the power dissipation limits are not exceeded. This applies to only
1 amplifier at a time for the dual op amp. Continuous operation
under these conditions may degrade long term reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28110 and ISL28210 are immune to output
phase reversal, out to 0.5V beyond the rail (VABS MAX) limit.
Beyond these limits, the device is still immune to reversal to 1V
beyond the rails but damage to the internal ESD protection
diodes can result unless these input currents are limited.
Maximizing Dynamic Signal Range
The amplifiers maximum undistorted output swing is a figure of
merit for precision, low distortion applications. Audio amplifiers
are a good example of amplifiers that require low noise and low
signal distortion over a wide output dynamic range. When these
applications operate from batteries, raising the amplifier supply
voltage to overcome poor output voltage swing has the penalty of
increased power consumption and shorter battery life. Amplifiers
whose input and output stages can swing closest to the power
supply rails while providing low noise and undistorted
performance, will provide maximum useful dynamic signal range
and longer battery life.
Rail-to-rail input and output (RRIO) amplifiers have the highest
dynamic signal range but their added complexity degrades input
noise and amplifier distortion. Many contain two input pairs, one
pair operating to each supply rail. The trade-offs for these are
increased input noise and distortion caused by non-linear input
bias current and capacitance when amplifying high impedance
sources. Their rail-to-rail output stages swing to within a few
millivolts of the rail, but output impedances are high so that their
output swing decreases and distortion increases rapidly with
increasing load current. At heavy load currents the maximum
output voltage swing of RRO op amps can be lower than a good
emitter follower output stage.
The ISL28110 and ISL28210 low noise input stage and high
performance output stage are optimized for low THD+N into
moderate loads over the full -40掳C to +125掳C temperature
range. Figures 21 and 22 show the 1kHz THD+N unity gain
performance vs output voltage swing at load resistances of 2k
and 600. Figure 45 shows the unity-gain THD+N performance
driving 600 from 卤5V supplies.
FIGURE 43. INPUT ESD DIODE CURRENT LIMITING
-
+
RIN-
RL
VIN-
V+
V-
RIN+
VIN+
FIGURE 44. INPUT OFFSET VOLTAGE AND BIAS CURRENT vs
COMMON MODE INPUT VOLTAGE
VCM (V)
N
O
R
M
A
L
IZ
E
D
IN
P
U
T
B
IA
S
C
U
R
E
N
T
(p
A
)
-10
-8
-6
-4
-2
0
2
4
6
8
10
-15
-10
-5
0
5
10
15
-500
-400
-300
-200
-100
0
100
200
300
400
500
N
O
R
M
A
L
IZ
E
D
V
O
S
(u
V
)
VS = 卤15V
T = +25掳C
INPUT OFFSET VOLTAGE (VOS)
INPUT BIAS (IB)
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ISL28110FBZ-T13 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28110FBZ SINGLE PRECISION LW NOISE RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V
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ISL28110FBZ-T7A 鍔熻兘鎻忚堪:鏀惧ぇ鍣� IC 闁嬬櫦(f膩)宸ュ叿 ISL28110FBZ SINGLE PRECISION LW NOISE RoHS:鍚� 鍒堕€犲晢:International Rectifier 鐢�(ch菐n)鍝�:Demonstration Boards 椤炲瀷:Power Amplifiers 宸ュ叿鐢ㄤ簬瑭曚及:IR4302 宸ヤ綔闆绘簮闆诲:13 V to 23 V
ISL28110FRTBZ 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers
ISL28110FRTZ 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers