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| 型號： | ISL28134IBZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP CHOPPER R-R 8SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 放大器類型： | 斷路器（零漂移） |
| 電路數(shù)： | 1 |
| 輸出類型： | 滿擺幅 |
| 轉(zhuǎn)換速率： | 1.5 V/µs |
| 增益帶寬積： | 3.5MHz |
| 電流 - 輸入偏壓： | 120pA |
| 電壓 - 輸入偏移： | 0.2µV |
| 電流 - 電源： | 675µA |
| 電流 - 輸出 / 通道： | 65mA |
| 電壓 - 電源，單路/雙路(±)： | 2.25 V ~ 6 V，±1.125 V ~ 3 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ISL28134IBZ-T7ADKR |
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ISL28134
15
FN6957.5
July 12, 2013
High Source Impedance Applications
The input stage of Chopper Stabilized amplifiers do not behave
like conventional amplifier input stages. The ISL28134 uses
switches at the chopper amplifier input that continually ‘chops’
the input signal at 100kHz to reduce input offset voltage down to
1V. The dynamic behavior of these switches induces a charge
injection current to the input terminals of the amplifier. The
charge injection current has a DC path to ground through the
resistances seen at the input terminals of the amplifier. Higher
input impedance cause an apparent shift in the input bias
current of the amplifier. Input impedances larger than 10k
begin to have significant increases in the bias currents. To
minimize the effect of impedance on input bias currents, an
input resistance of <10k is recommended.
Because the chopper amplifier has charge injection currents at
each terminal, the input impedance should be balanced across
each input (see Figure 44). The input impedance of the amplifier
should be matched between the IN+ and IN- terminals to
minimize total input offset current. Input offset currents show up
as an additional output offset voltage, as shown in Equation 1:
If the offset voltage of the amplifier is negative, the input offset
currents will add to the total output offset. For a 10,000V/V gain
amplifier using 1M feedback resistor, a 500pA total input offset
current will have an additional output offset voltage of 0.5mV. By
keeping the input impedance low and balanced across the
amplifier inputs, the input offset current is kept below 100pA,
resulting in an offset voltage 0.1mV or less.
IN+ and IN- Protection
The ISL28134 is capable of driving the input terminals up to and
beyond the supply rails by about 0.5V. Back biased ESD diodes
from the input pins to the V+ and V- rails will conduct current
when the input signals go more than 0.5V beyond the rail
(see Figure 45). The ESD protection diodes must be current
limited to 20mA or less to prevent damage of the IC. This current
can be reduced by placing a resistor in series with the IN+ and IN-
inputs in the event the input signals go beyond the rail.
EMI Rejection
Electromagnetic Interference (EMI) can be a problem in high
frequency applications for precision amplifiers. The Op-amp pins
are susceptible to EMI signals which can rectify high frequency
inputs beyond the amplifier bandwidth and present itself as a
shift in DC offset voltage. Long trace leads to Op-amp pins may
act as an antenna for radiated RF signals which result in a total
conductive EMI noise into the Op-amp inputs.
The most susceptible pin is the non-inverting IN+ input therefore
EMI rejection (EMIR) on this pin is important for RF type
applications. The ability of the amplifier output to reject EMI is
called EMI Rejection Ratio (EMIRR) and is computed as:
EMIRR (dB) = 20 log (VIN_PEAK/ ΔVOS
The test circuit for measuring the DC offset of the amplifier with
an RF signal input to the IN+ pin is show in Figure 46. The EMIRR
performance of the ISL28134 at the IN+ pin across a frequency
of 10MHz to 2.4GHz is plotted on Figure 33. The ISL28134 shows
a typical EMIRR of 75dB at 1GHz. For better EMI immunity, a
small RFI filter can be placed at the input to attenuate out of
band signals and reduce DC offset shift from high frequency RF
signals into the IN+ pin. For example, a 15 and 100pF RC filter
will roll off signals above 100MHz for better EMIRR performance.
TABLE 1.
PART
VOLTAGE NOISE @
100Hz
0.1Hz to 10Hz PEAK-TO-PEAK
VOLTAGE NOISE
Competitor A
22nV/√Hz
600nVP-P
Competitor B
16nV/√Hz
260nVP-P
Competitor C
90nV/√Hz
1500nVP-P
ISL28134
8nV/√Hz
250nVP-P
VOSTOT = VOS - RF*IOS
(EQ. 1)
FIGURE 44. CIRCUIT IMPLEMENTATION FOR REDUCING INPUT
BIAS CURRENTS
-
+
RF
RI
RS
+2.5V
-2.5V
VOUT
RL
RG
RS//RG = RS//RG
VIN
FIGURE 45. INPUT CURRENT LIMITING
-
+
RIN
RL
VIN
VOUT
V+
V-
ESD
DIODES
IN-
IN+
FIGURE 46. CIRCUIT TESTING EMIRR
-
+
RL= 10k
VIN = 200mVp-p
VOUT
IN-
IN+
-2.5V
+2.5V
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