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參數(shù)資料
| 型號： | ISL28177FBZ-T7A |
| 廠商： | Intersil |
| 文件頁數(shù)： | 13/15頁 |
| 文件大小： | 0K |
| 描述： | IC OPAMP GP 600KHZ SGL 8SOIC |
| 標準包裝： | 1 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 1 |
| 轉換速率： | 0.2 V/µs |
| 增益帶寬積： | 600kHz |
| 電流 - 輸入偏壓： | 200pA |
| 電壓 - 輸入偏移： | 150µV |
| 電流 - 電源： | 1.18mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 6 V ~ 40 V，±3 V ~ 20 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 標準包裝 |
| 其它名稱： | ISL28177FBZ-T7ADKR |
ISL28177
7
FN7859.2
April 5, 2012
Applications Information
Functional Description
The ISL28177 is a low noise op amp fabricated in a 40V
complementary bipolar DI process designed for general purpose
low power applications. It utilizes a super-beta NPN input stage
with input bias current cancellation for low input bias current and
low input noise voltage. A complimentary bipolar output stage
enables high capacitive load drive without external
compensation.
Operating Voltage Range
The ISL28177 is designed to operate over the 6V (±3V) to 40V
(±20V) range. The common mode input voltage range extends to
2V from each rail, and the output voltage swings to 1.3V of
each rail.
Input Performance
The super-beta NPN input pair reduces input bias current while
maintaining good frequency response, low input bias current and
low noise. Input bias cancellation circuits provide additional bias
current reduction to <1nA, and excellent temperature
stabilization and low TCVOS.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500 current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 21).
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dv/dt exceeds the
0.2V/s slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output, resulting in severe distortion and possible diode
failure. Figure 17 provides an example of distortion free large signal
response using a 10VP-P input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be equal
to the maximum power supply voltage (40V) without damage.
In applications where one or both amplifier input terminals are at
risk of exposure to high voltages beyond the power supply rails,
current limiting resistors may be needed at the input terminal to
limit the current through the power supply ESD diodes to
20mA max.
Output Current Limiting
The output current is internally limited to approximately ±30mA
at +25°C and can withstand a short circuit to either rail as long
as the power dissipation limits are not exceeded. Continuous
operation under these conditions may degrade long term
reliability.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28177 is immune to output phase reversal.
FIGURE 19. POSITIVE OUTPUT OVERLOAD RESPONSE TIME
FIGURE 20. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME
Typical Performance Curves V
S = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
-2
0
2
4
6
8
10
12
14
16
-280
-240
-200
-160
-120
-80
-40
0
40
80
0
40
80
120 160 200 240 280 320 360 400
O
U
T
P
U
T
(V
)
IN
P
U
T
(m
V
)
TIME (s)
VS = ±15V
AV = 100
VIN = 200mVP-P
OVERDRIVE = 1V
RL = 10k
INPUT
OUTPUT
-16
-14
-12
-10
-8
-6
-4
-2
0
2
-80
-40
0
40
80
120
160
200
240
280
0
40
80
120 160 200 240 280 320 360 400
O
U
T
P
U
T
(V
)
IN
P
U
T
(m
V
)
TIME (s)
VS = ±15V
AV = 100
VIN = 200mVP-P
OVERDRIVE = 1V
RL = 10k
INPUT
OUTPUT
FIGURE 21. INPUT ESD DIODE CURRENT LIMITING
-
+
RL
VIN
VOUT
V+
V-
500
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