16 FN6639.3 November 29, 2012 Power Dissipation It is possible to exceed the +150°C maximum junction temperatures under cert" />
參數(shù)資料
型號: ISL28210FBZ-T13
廠商: Intersil
文件頁數(shù): 8/23頁
文件大?。?/td> 0K
描述: IC OPAMP JFET 12.5MHZ DUAL 8SOIC
產(chǎn)品培訓模塊: Solutions for Industrial Control Applications
標準包裝: 2,500
放大器類型: J-FET
電路數(shù): 2
轉(zhuǎn)換速率: 20 V/µs
增益帶寬積: 12.5MHz
電流 - 輸入偏壓: 2pA
電壓 - 輸入偏移: 300µV
電流 - 電源: 2.55mA
電流 - 輸出 / 通道: 50mA
電壓 - 電源,單路/雙路(±): 9 V ~ 40 V,±4.5 V ~ 20 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應商設備封裝: 8-SOIC
包裝: 帶卷 (TR)
ISL28110, ISL28210
16
FN6639.3
November 29, 2012
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
where:
PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
PDMAX for each amplifier can be calculated using Equation 2:
where:
TMAX = Maximum ambient temperature
θJA = Thermal resistance of the package
PDMAX = Maximum power dissipation of 1 amplifier
VS = Total supply voltage
IqMAX = Maximum quiescent supply current of 1 amplifier
VOUTMAX = Maximum output voltage swing of the application
RL = Load resistance
ISL28110 and ISL28210 SPICE Model
Figure 46 shows the SPICE model schematic and Figure 47 shows
the net list for the SPICE model. The model is a simplified version
of the actual device and simulates important AC and DC
parameters. AC parameters incorporated into the model are: 1/f
and flatband noise voltage, Slew Rate, CMRR, Gain and Phase. The
DC parameters are IOS, total supply current and output voltage
swing. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 4. The AVOL is adjusted
for 125dB with the dominant pole at 7Hz. The CMRR is set 120dB,
f = 280kHz. The input stage models the actual device to present
an accurate AC representation. The model is configured for
ambient temperature of +25°C.
Figures 48 through 61 show the characterization vs simulation
results for the Noise Voltage, Closed Loop Gain vs Frequency,
Small Signal 0.1V Step, Large Signal 5V Step Response, Open
Loop Gain Phase, CMRR and Output Voltage Swing for ±5V and
±15V supplies.
LICENSE STATEMENT
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable licence to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
The Licensee may not sell, loan, rent, or license the macro-model,
in whole, in part, or in modified form, to anyone outside the
Licensee’s company. The Licensee may modify the macro-model
to suit his/her specific applications, and the Licensee may make
copies of this macro-model for use within their company only.
This macro-model is provided “AS IS, WHERE IS, AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental,
or consequential damages in connection with or arising out of
the use of this macro-model. Intersil reserves the right to make
changes to the product and the macro-model without prior
notice.
FIGURE 45. UNITY-GAIN THD+N vs OUTPUT VOLTAGE vs
TEMPERATURE AT VS = ±5V FOR 600Ω LOAD
0.0001
0.001
0.01
0.1
1
0
1
2
345
67
8
9
10
VP-P (V)
THD+N
(%)
VS = ±5V
RL = 600Ω
AV = 1
+25°C
0°C
-40°C
+125°C
+85°C
TJMAX
TMAX θJAxPDMAXTOTAL
+
=
(EQ. 1)
PDMAX
VS IqMAX VS
(
- VOUTMAX)
VOUTMAX
RL
----------------------------
×
+
×
=
(EQ. 2)
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