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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | ISL28210FBZ |
| 寤犲晢锛� | Intersil |
| 鏂囦欢闋佹暩(sh霉)锛� | 6/23闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC OPAMP JFET 12.5MHZ DUAL 8SOIC |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Solutions for Industrial Control Applications |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 97 |
| 鏀惧ぇ鍣ㄩ鍨嬶細 | J-FET |
| 闆昏矾鏁�(sh霉)锛� | 2 |
| 杞�(zhu菐n)鎻涢€熺巼锛� | 20 V/µs |
| 澧炵泭甯跺绌嶏細 | 12.5MHz |
| 闆绘祦 - 杓稿叆鍋忓锛� | 2pA |
| 闆诲 - 杓稿叆鍋忕Щ锛� | 300µV |
| 闆绘祦 - 闆绘簮锛� | 2.55mA |
| 闆绘祦 - 杓稿嚭 / 閫氶亾锛� | 50mA |
| 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±)锛� | 9 V ~ 40 V锛�±4.5 V ~ 20 V |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-SOIC锛�0.154"锛�3.90mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-SOIC |
| 鍖呰锛� | 绠′欢 |
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ISL28110, ISL28210
14
FN6639.3
November 29, 2012
Applications Information
Functional Description
The ISL28110 and ISL28210 are single and dual 12.5 MHz
precision JFET input op amps. These devices are fabricated in the
PR40 Advanced Silicon-on-Insulator (SOI) bipolar-JFET process to
ensure latch-free operation. The precision JFET input stage
provides low input offset voltage (300V max @ +25掳C), low
input voltage noise (6nV/
鈭欻z), and input current noise that is
very low with virtually no 1/f component. A high current
complementary NPN/PNP emitter-follower output stage provides
high slew rate and maintains excellent THD+N performance into
heavy loads (0.0003% @ 10VP-P @ 1kHz into 600惟).
Operating Voltage Range
The devices are designed to operate over the 9V (卤4.5V) to 40V
(卤20V) range and are fully characterized at 10V (卤5V) and 30V
(卤15V). The JFET input stage maintains high impedance over a
maximum input differential voltage range of 卤33V. Internal ESD
protection diodes clamp the non-inverting and inverting inputs to
one diode drop above and below the V+ and V- the power supply
rails (鈥淧in Descriptions鈥� on page 2, CIRCUIT 1).
Input ESD Diode Protection
The JFET gate is a reverse-biased diode with >33V reverse
breakdown voltage which enables the device to function reliably in
large signal pulse applications without the need for anti-parallel
clamp diodes required on MOSFET and most bipolar input stage
op amps. No special input signal restrictions are needed for
power supply operation up to 卤15V, and input signal distortion
caused by nonlinear clamps under high slew rate conditions are
avoided. For power supply operation greater than 卤16V (>32V),
the internal ESD clamp diodes alone cannot clamp the maximum
input differential signal to the power supply rails without the risk
of exceeding the 33V breakdown of the JFET gate. Under these
conditions, differential input voltage limiting is necessary to
prevent damage to the JFET input stage.
In applications where one or both amplifier input terminals are at
risk of exposure to voltages beyond the supply rails, current
limiting resistors may be needed at each input terminal (see
ESD diodes to 20mA.
FIGURE 39. LARGE SIGNAL 10V STEP RESPONSE AV = -1
FIGURE 40. LARGE SIGNAL 10V STEP RESPONSE AV = +10
FIGURE 41. SETTLING TIME (tS) vs CLOSED LOOP GAIN
FIGURE 42. ZOUT vs FREQUENCY
Typical Performance Curves
VS = 卤15V, VCM = 0V, RL = Open, T = +25掳C, unless otherwise specified. (Continued)
-6
-4
-2
0
2
4
6
01
23
45
67
8
9
10
V
O
U
T
(V
)
TIME (s)
VS = 卤15V
AV = -1
RL = 2k
CL = 4pF
VS = 卤15V
AV = +10
RL = 2k
CL = 4pF
-6
-4
-2
0
2
4
6
012
34
56
78
9
10
V
O
U
T
(V
)
TIME (s)
1
10
100
0.1
1
10
100
CLOSED LOOP GAIN (V/V)
SETTL
ING
TI
ME
(s
)
VS = 卤15V
0.01%
0.1%
VOUT = 10VP-P
RL = 2k
0.01
0.1
1
10
100
1000
10
100
1k
10k
100k
1M
10M
100M
Z
OU
T
(
)
FREQUENCY (Hz)
VS = 卤15V
G = 1
G = 10
G = 100
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| ISL28210FBZ-T13 | 鍔熻兘鎻忚堪:IC OPAMP JFET 12.5MHZ DUAL 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:75 绯诲垪:MicroAmplifier™ 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.03 V/µs 澧炵泭甯跺绌�:100kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:60µV 闆绘祦 - 闆绘簮:20µA 闆绘祦 - 杓稿嚭 / 閫氶亾:5mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.3 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOIC 鍖呰:绠′欢 |
| ISL28210FBZ-T7 | 鍔熻兘鎻忚堪:IC OPAMP JFET 12.5MHZ DUAL 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:75 绯诲垪:MicroAmplifier™ 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):1 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:0.03 V/µs 澧炵泭甯跺绌�:100kHz -3db甯跺:- 闆绘祦 - 杓稿叆鍋忓:1pA 闆诲 - 杓稿叆鍋忕Щ:60µV 闆绘祦 - 闆绘簮:20µA 闆绘祦 - 杓稿嚭 / 閫氶亾:5mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.3 V ~ 5.5 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-SOIC锛�0.154"锛�3.90mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-SOIC 鍖呰:绠′欢 |
| ISL28210FBZ-T7A | 鍔熻兘鎻忚堪:IC OPAMP JFET 12.5MHZ DUAL 8SOIC RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> Linear - Amplifiers - Instrumentation 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,500 绯诲垪:- 鏀惧ぇ鍣ㄩ鍨�:閫氱敤 闆昏矾鏁�(sh霉):2 杓稿嚭椤炲瀷:婊挎摵骞� 杞�(zhu菐n)鎻涢€熺巼:350 V/µs 澧炵泭甯跺绌�:180MHz -3db甯跺:320MHz 闆绘祦 - 杓稿叆鍋忓:12.5µA 闆诲 - 杓稿叆鍋忕Щ:800µV 闆绘祦 - 闆绘簮:15mA 闆绘祦 - 杓稿嚭 / 閫氶亾:85mA 闆诲 - 闆绘簮锛屽柈璺�/闆欒矾(±):2.5 V ~ 12.6 V锛�±1.25 V ~ 6.3 V 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-MSOP 鍖呰:甯跺嵎 (TR) |
| ISL28210FRTBZ | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers |
| ISL28210FRTZ | 鍒堕€犲晢:INTERSIL 鍒堕€犲晢鍏ㄧū:Intersil Corporation 鍔熻兘鎻忚堪:Precision Low Noise JFET Operational Amplifiers |
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