19 November 30, 2012 FN6632.10 Applications Information Functional Description The ISL28117, ISL28217 and ISL28417" />
參數資料
型號: ISL28417FVZ
廠商: Intersil
文件頁數: 11/34頁
文件大?。?/td> 0K
描述: IC OPAMP 1.5MHZ QUAD LP 14TSSOP
標準包裝: 1,000
放大器類型: 通用
電路數: 4
轉換速率: 0.5 V/µs
增益帶寬積: 1.5MHz
電流 - 輸入偏壓: 80pA
電壓 - 輸入偏移: 10µV
電流 - 電源: 440µA
電流 - 輸出 / 通道: 43mA
電壓 - 電源,單路/雙路(±): 4.5 V ~ 40 V,±2.25 V ~ 20 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 14-TSSOP
包裝: 管件
ISL28117, ISL28217, ISL28417
19
November 30, 2012
FN6632.10
Applications Information
Functional Description
The ISL28117, ISL28217 and ISL28417 are single, dual and
quad, low noise precision op amps. Both devices are fabricated
in a new precision 40V complementary bipolar DI process. A
super-beta NPN input stage with input bias current cancellation
provides low input bias current (180pA typical), low input offset
voltage (13V typical), low input noise voltage (8nV/
√Hz), and
low 1/f noise corner frequency (~8Hz). These amplifiers also
feature high open loop gain (18kV/mV) for excellent CMRR
(145dB) and THD+N performance (0.0005% @ 3.5VRMS, 1kHz
into 2k
Ω). A complimentary bipolar output stage enables high
capacitive load drive without external compensation.
Operating Voltage Range
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). The Power Supply Rejection Ratio typically exceeds
140dB over the full operating voltage range and 120dB
minimum over the -40°C to +125°C temperature range. The
worst case common mode input voltage range over temperature
is 2V to each rail. With ±15V supplies, CMRR performance is
typically >130dB over-temperature. The minimum CMRR
performance over the -40°C to +125°C temperature range is
>120dB for power supply voltages from ±5V (10V) to ±15V (30V).
Input Performance
The super-beta NPN input pair provides excellent frequency
response while maintaining high input precision. High NPN beta
(>1000) reduces input bias current while maintaining good
frequency response, low input bias current and low noise. Input
bias cancellation circuits provide additional bias current
reduction to <1nA, and excellent temperature stabilization.
Figures 11 through 18 show the high degree of bias current
stability at ±5V and ±15V supplies that is maintained across the
-40°C to +125°C temperature range. The low bias current TC
also produces very low input offset current TC, which reduces DC
input offset errors in precision, high impedance amplifiers.
The +25°C maximum input offset voltage (VOS) for the “B” grade is
50V and 100V for the “C” grade. Input offset voltage temperature
coefficients (VOSTC) are a maximum of ±0.6V/°C for the “B” and
±0.9V/°C for the “C” grade. Figures 3 through 6 show the typical
gaussian-like distribution over the ±5V to ±15V supply range and over
the full temperature range. The VOS temperature behavior is smooth
(Figures 7 through 10) maintaining constant TC across the entire
temperature range.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails, series connected
500
Ω current limiting resistors and an anti-parallel diode pair
across the inputs (Figure 54).
The series resistors limit the high feed-through currents that can
occur in pulse applications when the input dV/dT exceeds the
0.5V/s slew rate of the amplifier. Without the series resistors, the
input can forward-bias the anti-parallel diodes causing current to
flow to the output resulting in severe distortion and possible diode
failure. Figure 48 provides an example of distortion free large signal
response using a 4VP-P input pulse with an input rise time of <1ns.
The series resistors enable the input differential voltage to be equal
to the maximum power supply voltage (40V) without damage.
FIGURE 53. COMMON MODE INPUT IMPEDANCE
Typical Performance Curves V
S = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
1
10
100
1k
10k
100k
1M
10M
100M
1
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0.1
IN
P
U
T
RES
IS
T
ANCE
(k
Ω
)
0.01
FIGURE 54. INPUT ESD DIODE CURRENT LIMITING- UNITY GAIN
-
+
RL
VIN
VOUT
V+
V-
500
Ω
500
Ω
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