5 FN7560.5 December 19, 2013 Ready Delay, On-Off tREADY-HL ISL33001" />
參數(shù)資料
型號： ISL33003IUZ-T
廠商： Intersil
文件頁數(shù)： 14/18頁
文件大?。?/td> 0K
描述： IC BUS BUFF HOTSWAP 2WR 8MSOP
標(biāo)準(zhǔn)包裝： 2,500
類型： 緩沖器
Tx/Rx類型： I²C Logic
電容 - 輸入： 10pF
電源電壓： 2.3 V ~ 5.5 V
電流 - 電源： 4mA
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 帶卷 (TR)
配用： ISL33003MSOPEVAL1Z-ND - EVAL BOARD ISL33003 8MSOP
ISL33001, ISL33002, ISL33003
5
FN7560.5
December 19, 2013
Ready Delay, On-Off
tREADY-HL
ISL33001 only (Note 10)
+25
-
10
-
ns
Ready Delay, Off-On
tREADY-LH
ISL33001 only (Note 10)
+25
-
10
-
ns
Ready Output Low Voltage
VOL_READY VCC1 = +2.5V, IPULLUP = 3mA; ISL33001 only
Full
-
0.4
V
RISE-TIME ACCELERATORS
Transient Accelerator
Current
ITRAN_ACC VCC1 = 2.7V, VCC2 = 2.7V; (ACC = 0.7*VCC1 for
ISL33002 only) (Figure 8)
+25
-
5
-
mA
Accelerator Enable
Threshold
VACC_EN
ISL33002 only
+25
-
0.5*VCC1
0.7*VCC1
V
Accelerator Disable
Threshold
VACC_DIS
ISL33002 only
+25
0.3*VCC1
0.5*VCC1
-
V
Accelerator Pin Input
Current
IACC
ISL33002 only
+25
-1
0.1
1
A
Accelerator Delay, On-Off
tPDOFF
ISL33002 only (Note 10)
+25
-
10
-
ns
ESD PROTECTION
SDA, SCL I/O Pins
Human Body Model, SDA and SCL pins to ground
only (JESD22-A114)
+25
-
±12
-
kV
All Pins
Machine Model (JESD22-A115)
+25
-
±400
-
V
Class 3 HBM ESD (JESD22-A114)
+25
±6
-
kV
INPUT-OUTPUT CONNECTIONS
Input Low Threshold
VIL
VCC1 = VCC2, 10kΩ to VCC1 on SDA and SCL pins
+25
-
0.3*VCC1
-V
Input-Output Offset
Voltage
VOS
VCC1 = 3.3V, 10kΩ to VCC1 on SDA and SCL pins,
VINPUT = 0.2V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 5)
Full
0
50
150
mV
Output Low Voltage
VOL
VCC1 = 2.7V, VINPUT = 0V, ISINK =3mA on
SDA/SCL pins; VCC2 = 2.7V, ISL33002 and
ISL33003 (Figure 6)
Full
-
0.4
V
Buffer SDA and SCL Pins
Input Capacitance
CIN
(Figure 25)
+25
-
10
-
pF
Input Leakage Current
ILEAK
SDA and SCL pins = VCC1 = 5.5V;
VCC2 = 5.5V, ISL33002 and ISL33003
Full
-5
0.1
5
A
TIMING CHARACTERISTICS
SCL/SDA Propagation
Delay High-to-Low
tPHL
CLOAD = 100pF, 2.7kΩ to VCC1 on SDA and SCL
pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
+25
0
27
100
ns
SCL/SDA Propagation
Delay Low-to-High
tPLH
CLOAD = 100pF, 2.7kΩ to VCC1 on SDA and SCL
pins, VCC1 = 3.3V; VCC2 = 3.3V, ISL33002 and
ISL33003 (Figure 7)
+25
0
2
26
ns
NOTES:
8. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
9. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
10. Typical value determined by design simulations. Parameter not tested.
11. Buffer is in the connected state.
12. ISL33002 and ISL33003 limits established by characterization. Not production tested.
13. If the VCC1 and VCC2 voltages diverge, then the shut-down ICC increases on the higher voltage supply.
Electrical Specifications VEN = VCC1, VCC1 = +2.3V to +5.5V, VCC2 = +2.3V to +5.5V, unless otherwise noted (Note 8). Boldface limits apply
over the operating temperature range, -40°C to +85°C. (Continued)
PARAMETER
SYMBOL
CONDITIONS
TEMP
(°C)
MIN
(Note 9)
TYP
MAX
(Note 9)
UNITS
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