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參數(shù)資料
| 型號(hào)： | ISL35111DRZ-EVALZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BAORD FOR ISL35111DRZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
ISL35111
7
FN6975.2
July 19, 2012
Application Information
The typical application schematic for ISL35111 is shown in Figure 8.
PCB Layout Considerations
Because of the high speed of the ISL35111 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
All high speed differential pair traces should have a
characteristic impedance of 50
Ω with respect to ground plane
and 100
Ω with respect to each other.
Avoid using vias for high speed traces as this will create
discontinuity in the traces characteristic impedance.
Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
For each differential pair, the positive trace and the negative
trace need to be of same length in order to avoid intra-pair
skew. Serpentine technique may be used to match trace
lengths.
Maintain a constant solid ground plane underneath the
high-speed differential traces
Each VDD pin should be connected to 1.2V and also bypassed
to ground through a 47nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the VDD pin
and the bypass capacitors in order to maximize the power
supply noise rejection.
About Q:ACTIVE
Intersil has long realized that to enable the complex server
clusters of next generation datacenters, it is critical to manage
the signal integrity issues of electrical interconnects. To address
this, Intersil has developed its groundbreaking Q:ACTIVE
product line. By integrating its analog ICs inside cabling
interconnects, Intersil is able to achieve unsurpassed
improvements in reach, power consumption, latency, and cable
gauge size as well as increased airflow in tomorrow's
datacenters. This new technology transforms passive cabling into
intelligent "roadways" that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing cabling
while reducing the need for thicker cables. This significantly
reduces cable weight and clutter, increases airflow, and improves
power consumption.
FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL35111
NOTES:
12. See “Adjustable De-Emphasis” on page 6 for information on how to connect the DE pins
13. See “Line Silence/Quiescent Mode” on page 6 for details on DT pin operation.
14. Although the filtering network is shown only for one VDD pin for simplicity, all the VDD pins need to be connected in this way.
TDSBL
DT
DEA
DEB
1.2V
47nF
ISL35111
IN_P
2
IN_N
3
DT
15
VDD
1
VDD
9
VDD
12
OUT_N
10
OUT_P
11
LO
S
14
TDSBL
4
GND
16
GND
5
DE
A
6
DE
B
7
GND
8
GND
13
100nF
100pF
100nF
OUTPUT SIGNAL
INPUT SIGNAL
LOS (output)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL35111DRZ-T7 | 功能描述:接口 - 專用 ISL35111DRZFREE 11 1GB/S SNGL TRNSMITR RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| ISL35111DRZ-TS | 功能描述:接口 - 專用 ISL35111DRZFREE 11 1GB/S SNGL TRNSMITR RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| ISL35411 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Driver |
| ISL35411DRZ-EVALZ | 功能描述:EVAL BAORD FOR ISL35411DRZ RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:* 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| ISL35411DRZ-T7 | 功能描述:接口 - 專用 ISL36111DRZFREE 11 1GB/S SNGLCVR 100PCS RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
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