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參數(shù)資料
| 型號(hào)： | ISL35411DRZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 5/11頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DVR QUAD 46QFN |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 應(yīng)用： | 以太網(wǎng) |
| 電源電壓： | 1.1 V ~ 1.3 V |
| 封裝/外殼： | 46-WFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 46-TQFN |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
ISL35411
3
FN6971.1
March 25, 2010
Pin Descriptions
PIN NAME
PIN NUMBER
DESCRIPTION
VDD
1, 5, 9, 13, 24,
27, 28, 31, 32,
35, 36, 39
Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors
to ground is recommended for each of these pins for broad high-frequency noise suppression.
IN1[P,N]
2, 3
Driver 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
TDSBL1
4
Transmit disable pin for Driver 1. Disables the driver when pulled to VDD. Connected to
ground for normal operation.
IN2[P,N]
6, 7
Driver 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
TDSBL2
8
Transmit disable pin for Driver 2. Disables the driver when pulled to VDD. Connected to
ground for normal operation.
IN3[P,N]
10, 11
Driver 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
TDSBL3
12
Transmit disable pin for Driver 3. Disables the driver when pulled to VDD. Connected to
ground for normal operation.
IN4[P,N]
14, 15
Driver 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
TDSBL4
16
Transmit disable pin for Driver 4. Disables the driver when pulled to VDD. Connected to
ground for normal operation.
GND
17, 23, 40, 46
These pins should be grounded.
DT2
18
Detection Threshold for drivers 3 and 4. Reference DC voltage threshold for input signal
power detection. Data outputs OUT3 and OUT4 are muted when the power of IN3 and IN4,
respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and
always enable the limiting amplifier.
DE2[A,B,]
19, 20
Control pins for setting de-emphasis on drivers 3 and 4. CMOS logic inputs. Pins are read
as a 2-digit number to set the de-emphasis level. A is the MSB, and B is the LSB. Pins are
internally pulled up and pulled down with 25kΩ resistors.
NC
21, 22, 41, 45
Not connected: Do not make any connections to these pins.
OUT4[N,P]
25, 26
Driver 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT3[N,P]
29, 30
Driver 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT2[N,P]
33, 34
Driver 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
OUT1[N,P]
37, 38
Driver 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least
6GHz frequency response is recommended.
DE1[B,A]
42, 43
Control pins for setting de-emphasis on drivers 1 and 2. CMOS logic inputs. Pins are read
as a 2-digit number to set the de-emphasis level. A is the MSB, and B is the LSB. Pins are
internally pulled up and pulled down with 25kΩ resistors.
DT1
44
Detection Threshold for drivers 1 and 2. Reference DC voltage threshold for input signal
power detection. Data outputs OUT1 and OUT2 are muted when the power of IN1 and IN2,
respectively, fall below the threshold. Tie to ground to disable electrical idle preservation and
always enable the limiting amplifier.
Exposed Pad
-
Exposed ground pad. For proper electrical and thermal performance, this pad should be
connected to the PCB ground plane.
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