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參數(shù)資料
| 型號： | ISL36111DRZ-EVALZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD FOR ISL36111DRZ |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
ISL36111
7
FN6974.2
July 19, 2012
Application Information
Typical application schematic for ISL36111 is shown in Figure 8.
PCB Layout Considerations
Because of the high speed of the ISL36111 signals, careful PCB
layout is critical to maximize performance. The following
guidelines should be adhered to as closely as possible:
All high speed differential pair traces should have a
characteristic impedance of 50
Ω with respect to ground plane
and 100
Ω with respect to each other.
Avoid using vias for high speed traces as this will create
discontinuity in the traces characteristic impedance.
Input and output traces need to have DC blocking capacitors
(100nF). Capacitors should be placed as close to the chip as
possible.
For each differential pair, the positive trace and the negative
trace need to be of same length in order to avoid intra-pair
skew. Serpentine technique may be used to match trace
lengths.
Maintain a constant solid ground plane underneath the high-
speed differential traces
Each VDD pin should be connected to 1.2V and also bypassed
to ground through a 47nF and a 100pF capacitor in parallel.
Minimize the trace length and avoid vias between the VDD pin
and the bypass capacitors in order to maximize the power
supply noise rejection.
About Q:ACTIVE
Intersil has long realized that to enable the complex server
clusters of next generation datacenters, it is critical to manage
the signal integrity issues of electrical interconnects. To address
this, Intersil has developed its groundbreaking Q:ACTIVE
product line. By integrating its analog ICs inside cabling
interconnects, Intersil is able to achieve unsurpassed
improvements in reach, power consumption, latency, and cable
gauge size as well as increased airflow in tomorrow’s
datacenters. This new technology transforms passive cabling into
intelligent “roadways” that yield lower operating expenses and
capital expenditures for the expanding datacenter.
Intersil Lane Extenders allow greater reach over existing cabling
while reducing the need for thicker cables. This significantly
reduces cable weight and clutter, increases airflow, and improves
power consumption.
FIGURE 8. TYPICAL APPLICATION REFERENCE SCHEMATIC FOR ISL36111
NOTES:
14. See “Control Pin Boost Setting” on page 5 for information on how to connect the CP pins
15. See “Detection Thereshold (DT) Pin Functionality” on page 6 for details on DT pin operation.
16. Although the filtering network is shown only for one VDD pin for simplicity, all the VDD pins need to be connected in this way.
DT
CPA
CPB
LOSB (output)
1.2V
47nF
ISL36111
IN_P
2
IN_N
3
DT
15
VDD
1
VDD
9
VDD
12
OUT_N
10
OUT_P
11
NC
14
LOSB
4
GND
16
GND
5
CP
A
6
CPB
7
GND
8
GND
13
100nF
100pF
100nF
INPUT SIGNAL
OUTPUT SIGNAL
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| ISL36111DRZ-T7 | 功能描述:IC EQUALIZER REC 11.1GBPS 16QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:QLx™ 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| ISL36111DRZ-TS | 功能描述:IC EQUALIZER REC 11.1GBPS 16QFN RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:QLx™ 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| ISL36356A-APDK | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PRISM 11Mbps Wireless Local Area Network Access Point |
| ISL36356A-APDK-EVAL | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:PRISM 11Mbps Wireless Local Area Network Access Point |
| ISL36411 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Quad Lane Extender |
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