參數(shù)資料
型號(hào)： ISL3873A
廠商： Intersil Corporation
元件分類(lèi)： 基帶處理器
英文描述： Wireless LAN Integrated Medium Access Controller with Baseband Processor
中文描述： 集成的無(wú)線(xiàn)局域網(wǎng)媒體訪(fǎng)問(wèn)控制器基帶處理器
文件頁(yè)數(shù)： 36/42頁(yè)
文件大?。?/td> 778K
代理商： ISL3873A
36
CONFIGURATION REGISTER 23 ADDRESS (2Eh) R/W AGC TABLE DATA
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bits 6:0
AGC look up table data, unsigned.
CONFIGURATION REGISTER 24 ADDRESS (30h) R/W AGC LOOP GAIN
Bits 7
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 6:0
AGC loop gain (0.xxxx - x.00000, 0 - 1.0000 range), nominally 0.7.
CONFIGURATION REGISTER 25 ADDRESS (32h) R/W AGC RX_IF AND RF
Bits 7
AGC RX_RF, This input drives the RX-RF control if AGC override Enable is set to 1.
When Polarity bit (CR26[6]) is zero:
1 = removes 30dB pad.
0 = inserts 30dB pad.
Bits 6:0
AGC RX_IF, This CR is input to RF-IF DAC if AGC override Enable (CR 26[2]) is set to 1.
CONFIGURATION REGISTER 26 ADDRESS (34h) R/W AGC TEST MODES
Bits 7
AGC continuous update.
0 = disable, no updates during AGC freeze.
1 = allow updates during freeze AGC and AGC_lock.
See also CR17[7].
Bit 6
rxRFAGC polarity control.
0 = normal.
1 = invert.
Bit 5
AGC extra update disable. Allows final 32 sample update tweak after AGC_lock is declared.
0 = enable an extra update.
1 = disable extra update.
Bits 3:4
R/W but not currently used internally, should be set to zero to ensure compatibility with future revisions.
Bit 2
AGC override Enable.
0 = normal, disabled.
1 = enabled, CR25 controls receiver gain in both RF and IF via RXRF_AGC and RXIF_AGC lines.
Bit 1
AGC 2nd antenna power abort.
0 = AGC lock on 2nd antenna is required to finish antenna dwell.
1 = abort 2nd antenna lock search immediately if power is lower on 2nd antenna than on 1st antenna.
Bit 0
AGC Sat Step disable if within CR29[7:5] window.
0 = disable sat step.
1 = enable sat step.
CONFIGURATION REGISTER ADDRESS 27 (36h) R/W AGC RF THRESHOLD
Bit 7
RXRF AGC disable.
0 = normal.
1 = disables threshold.
Bits 6:0
RF AGC threshold (0-64 range). The RxRf_Agc pad is removed if the AGC voltage falls below this threshold.
CONFIGURATION REGISTER ADDRESS 28 (38h) R/W AGC LOW SAT ATTENUATOR
Bits 7:4
Mid saturation attenuation (0-30 range). Note: mid saturation attenuation is programmed as this value times 2. The mid and
low attenuator steps will occur if the number of I and Q saturations are greater than the mid and low saturation counts set by
CR16.
Bits 3:0
low saturation attenuation (0-15 range).
CONFIGURATION REGISTER ADDRESS 29 (3Ah) R/W AGC LOCK WINDOW NEGATIVE SIDE
Bits 7:5
AGC Saturation Block Level, 1xx.x, range 4.0 to 7.5 dB. Disable saturation attenuation step if less than or equal to this level.
Bits 4:0
AGC lock window negative side. (0-15.5 range) (this is the outer lock window) Note: set as a positive number, logic will convert
to negative.
ISL3873A
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