參數(shù)資料
型號(hào)： ISL3873AIK
廠商： INTERSIL CORP
元件分類： 微控制器/微處理器
英文描述： RES 0805 1/8W 5% 1.2KOHM
中文描述： 1 CHANNEL(S), 11M bps, LOCAL AREA NETWORK CONTROLLER, PBGA192
封裝： 14 X 14 MM, PLASTIC, BGA-192
文件頁(yè)數(shù)： 31/42頁(yè)
文件大小： 778K
代理商： ISL3873AIK
Control Registers
The following tables describe the function of each control register along with the associated bits in each control register.
CONFIGURATION REGISTER 0 ADDRESS (0h) R PART/VERSION CODE
Bit 7:4
Part Code
3 = HFA3863 series
Bit 3:0
Version Code
0 = 3863 Version
CONFIGURATION REGISTER 1 ADDRESS (02h) R/W I/O POLARITY
This register is used to define the phase of clocks and other interface signals. 00h is normal setting.
Bit 7
This control bit selects the phase of the receive carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q in.
Logic 0 = normal rotation (CCW).
Bit 6
This control bit selects the phase of the transmit carrier rotation sense.
Logic 1 = Inverted rotation (CW), Invert Q out.
Logic 0 = normal rotation (CCW).
Bit 5
This control bit selects the phase of the transmit output clock (TXCLK) pin.
Logic 1 = Inverted TXCLK.
Logic 0 = NON-Inverted TXCLK.
Bit 4
This control bit selects the active level of the Transmit Ready (TX_RDY) output which is an output pin at the test port, pin.
Logic 1 = TX_RDY Active 0.
Logic 0 = TX_RDY Active 1.
Bit 3
This control bit selects the active level of the transmit enable (TX_PE) input pin.
Logic 1 = TX_PE Active 0.
Logic 0 = TX_PE Active 1.
Bit 2
This control bit selects the active level of the Clear Channel Assessment (CCA) output pin.
Logic 1 = CCA Active 1.
Logic 0 = CCA Active 0.
Bit 1
This control bit selects the active level of the MD_RDY output pin.
Logic 1 = MD_RDY is Active 0.
Logic 0 = MD_RDY is Active 1.
Bit 0
This controls the phase of the RX_CLK output.
Logic 1 = Invert Clk.
Logic 0 = Non-Inverted Clk.
CONFIGURATION REGISTER 2 ADDRESS (04h) R/W RX CONFIGURE
Write to control, Read to verify control, setup while TX_PE and RX_PE are low
Bits 7:1
Reserved.
Bit 0
Initialization.
0 = Normal Operation.
1 = Soft Initialization of learned behavior registers such as DCoffset, NoiseFloor, FAR, RecPacketsNOcs1, and
RecPacketsUSEdef. Holds AGC logic reset. At part initialization, must be set, then after CR47 is loaded, cleared.
CONFIGURATION REGISTER 3 ADDRESS (06h) R/W TX PREAMBLE LENGTH FOR SHORT PREAMBLE
Bits 0 - 7
Thisregister contains the count for the Preamble length counter for short preamblesselected byCR5 bit 3. Setup while TX_PE
is low. For IEEE 802.11 use38h. For other than IEEE 802.11 applications, in general increasing the preamble length will improve
low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value is 56d = 38h. A 2
symbol TX power amplifier ramp up is added to programmed value.
CONFIGURATION REGISTER 4 ADDRESS (08h) R/W TX PREAMBLE LENGTH FOR LONG PREAMBLE
Bits 0 - 7
This register contains the count for the Preamble length counter for long preambles selected with CR5 bit 3 or CR11 bit 4.
Setup while TX_PE is low.
For IEEE 802.11 use 80h
. ForotherthanIEEE802.11applications,ingeneralincreasingthe preamble
length will improve low signal to noise acquisition performance at the cost of greater link overhead. The minimum suggested value
is 56d = 38h. A 2 symbol TX power amplifier ramp up is added to programmed value. If you program 128 you get 130.
ISL3873A
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ISL3873AIK-TK 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor
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