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參數(shù)資料
| 型號： | ISL3874 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基帶處理器 |
| 英文描述： | Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
| 中文描述： | 集成的無線局域網(wǎng)媒體訪問控制器的基帶微型處理器的PCI |
| 文件頁數(shù)： | 21/33頁 |
| 文件大?。?/td> | 390K |
| 代理商： | ISL3874 |
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21
For the 1 and 2Mbps modes, the transmitter accepts data
from the external source, scrambles it, differentially encodes
it as either DBPSK or DQPSK, and spreads it with the BPSK
PN sequence. The baseband digital signals are then output
to the external IF modulator.
For the CCK modes, the transmitter inputs the data and
partitions it into nibbles (4 bits) or bytes (8 bits). At 5.5Mbps, it
uses two of those bits to select one of 4 complex spread
sequences from a table of CCK sequences and then QPSK
modulates that symbol with the remaining 2 bits. Thus, there
are 4 possible spread sequences to send at four possible
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase reference
for the data portion of the packet is the phase of the last bit of
the header. At 11Mbps, one byte is used as above where 6 bits
are used to select one of 64 spread sequences for a symbol
and the other 2 are used to QPSK modulate that symbol. Thus,
the total possible number of combinations of sequence and
carrier phases is 256. Of these only one is sent.
The bit rate Table 15 shows examples of the bit rates and
the symbol rates and Figure 12 shows the modulation
schemes.
Header/Packet Description
The ISL3874 is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions. The
ISL3874 generates its own preamble and header information. It
uses two packet preamble and header configurations. The first
is backwards compatible with the existing IEEE 802.11-1997 1
and 2Mbps modes and the second is the optional shortened
mode which maximizes throughput at the expense of
compatibility with legacy equipment.
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1’s
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
802.11 DSSS BPSK
1Mbps
BARKER
802.11 DSSS QPSK
2Mbps
BARKER
DATA
I
OUT
Q
OUT
CHIP
RATE
1 BIT ENCODED TO
ONE OF 2 CODE
WORDS
(TRUE-INVERSE)
2 BITS ENCODED
TO ONE OF
4 CODE WORDS
SYMBOL
RATE
I vs. Q
11 MC/S
11 MC/S
1 MS/S
1 MS/S
11 CHIPS
11 CHIPS
FIGURE 12. MODULATION MODES
5.5Mbps CCK
COMPLEX
SPREAD FUNCTIONS
4 BITS ENCODED
TO ONE OF 16
COMPLEX CCK
CODE WORDS
11 MC/S
1.375 MS/S
8 CHIPS
11Mbps CCK
COMPLEX
SPREAD FUNCTIONS
8 BITS ENCODED
TO ONE OF 256
COMPLEX CCK
CODE WORDS
11 MC/S
1.375 MS/S
8 CHIPS
TABLE 15. BIT RATE TABLE EXAMPLES FOR MCLK = 44MHz
DATA
MODULATION
A/D SAMPLE CLOCK
(MHz)
TX SETUP CR 5
BITS 1, 0
RX SIGNAL CR 63
BITS 7, 6
DATA RATE
(Mbps)
SYMBOL RATE
(MSPS)
DBPSK
22
00
00
1
1
DQPSK
22
01
01
2
1
CCK
22
10
10
5.5
1.375
CCK
22
11
11
11
1.375
ISL3874
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| ISL3874IK | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI |
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