參數(shù)資料
型號: ISL3874IK
廠商: INTERSIL CORP
元件分類: 微控制器/微處理器
英文描述: Wireless LAN Integrated Medium Access Controller with Baseband Processor with Mini-PCI
中文描述: 1 CHANNEL(S), 11M bps, LOCAL AREA NETWORK CONTROLLER, PBGA192
封裝: 14 X 14 MM, PLASTIC, BGA-192
文件頁數(shù): 28/33頁
文件大小: 390K
代理商: ISL3874IK
28
to 2 bits. In the CCK mode, when a symbol decision error is
made, up to 6 bits may be in error although on average only 3
bits will be in error. Secondly, when the bits are processed by
the descrambler, these errors are further extended. The
descrambler is a 7-bit shift register with two taps exclusive or’ed
with the bit stream. Thus, each error is extended by a factor of
three. Multiple errors can be spaced the same as the tap
spacing, so they can be canceled in the descrambler. In this
case, two wrongs do make a right. Given all that, if a single
error is made the whole packet is discarded anyway, so the
error extension property has no effect on the packet error rate.
It should be taken into account if a forward error correction
scheme is contemplated.
Descrambling is self synchronizing and is done by a
polynomial division using a prescribed polynomial. A shift
register holds the last quotient and the output is the exclusive-
or of the data and the sum of taps in the shift register.
PREAMBLE/HEADER
CRC-16
GENERATOR
TX_AGC_IN
V
REF
I
REF
ANTSEL
TX_DATA
SCRAMBLER
TXD
P
MODULATOR,
BARKER/CCK
TXI
TXQ
TIMING
GENERATOR
MCLK
V
DD
(ANALOG)
V
DD
(DIGITAL)
GND (ANALOG)
GND (DIGITAL)
TXCLK
TX_RDY
TX_PE
ANTSEL
T
P
BBP_CLK
FIGURE 16. DSSS BASEBAND PROCESSOR, TRANSMIT SECTION
TX AGC
CONTROL
TRANSMIT
FILTER
O
T
O
DAC
DAC
TX
STATE
CONTROL
TX_IF_AGC
6-BIT
DAC
REGISTER
6-BIT
ADC
MAC
CONTROL
SIGNALS
I
T0 + 1
SYMBOL CORRELATOR
OUTPUT REPEATS
CORRELATION
PEAK
T0 + 2
SYMBOLS
T0
SAMPLES
AT 2X CHIP
RATE
EARLY
ON-TIME
LATE
CORRELATION TIME
FIGURE 17. CORRELATION PROCESS
CORRELATOR OUTPUT IS THE RESULT OF CORRELATING
THE PN SEQUENCE WITH THE RECEIVED SIGNAL
ISL3874
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