參數(shù)資料
型號(hào): ISL54105ACRZ
廠商: Intersil
文件頁數(shù): 13/16頁
文件大?。?/td> 0K
描述: IC TMDS REGENERATOR 72-QFN
標(biāo)準(zhǔn)包裝: 1,680
應(yīng)用: 多媒體顯示器,測(cè)試設(shè)備
接口: I²C
電源電壓: 3 V ~ 3.6 V
封裝/外殼: 72-WFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 72-QFN(10x10)
包裝: 托盤
安裝類型: 表面貼裝
6
FN6716.0
June 4, 2008
Register Listing
ADDRESS
REGISTER (DEFAULT VALUE)
BIT(S)
FUNCTION NAME
DESCRIPTION
0x00
Device ID (read only)
3:0
Device Revision
1 = initial silicon, 2 = second revision, etc.
7:4
Device ID
3 = ISL54105A
0x01
Channel Activity Detect (read only)
1:0
Reserved
2
Activity Detect
0: TMDS clock not present on RXC
1: TMDS clock detected on RXC
0x02
Channel Selection (0x0C)
3:0
Reserved
This nibble should always be set to 0xC.
4
Reset
Full chip reset. Write a 1 to reset. Will set itself to 0 when
reset is complete.
5
Power-down
0: Normal Operation
1: Puts the chip in a minimal power consumption mode,
turning off all TMDS outputs and open-circuiting all TMDS
inputs.
This bit is OR'ed with the Power-down input pin. If either is
set, the chip will enter power-down. Serial
I/O stays operational in PD mode.
Note: When exiting Power-down, a termination resistor
Recalibration cycle must be run to re-trim the termination
resistors (see register 0x03[7]).
0x03
Input Control (0x12)
Recommended default: 0x63
0
Reserved
Set to 1. Default value of 0 is OK, set to 1 to slightly reduce
power consumption.
1
Reserved
Set to 1.
2
Tri-state Clock
Inputs
0: Clock inputs are terminated into 50
Ω/100Ω.
1: Clock inputs are tri-stated (to allow chip to operate in
parallel with another TMDS receiver with fixed 50
Ω
termination)
3
Tri-state Data Inputs
0: Data inputs are terminated into 50
Ω/100Ω.
1: Data inputs are tri-stated (to allow chip to operate in
parallel with another TMDS receiver with fixed 50
Ω
termination)
4
Activity Detect Mode 0: AC Activity. Activity detection is based on the presence of
AC activity on TMDS clock inputs. This setting (along with a
hysteresis of 20mV enabled) provides reliable activity
detection. (recommended setting)
1: Common Mode Voltage. If the common mode voltage is
above ~3.05V, the input is considered in active. This method
has been found to be unreliable with small signal swings and
should not be used. This setting is the silicon default but
should be changed in software for more reliable activity
detection.
5
Clock Rx Hysteresis
Enables hysteresis for the clock inputs to prevent false clock
detection when both inputs are high. Data inputs do not get
hysteresis.
0: TMDS input hysteresis disabled
1: TMDS input hysteresis enabled. Eliminates false activity
detects on unconnected channels. (recommended setting)
6
Clock Rx Hysteresis
Magnitude
Controls the amount of hysteresis in the clock inputs.
0: 10mV
1: 20mV (recommended setting)
7
Recalibrate
0: Normal Operation
1: Recalibrates termination resistance. To recalibrate, take
this bit high, wait at least 1ms, then take this bit low.
Calibration is automatically done after power-on, but
performing a recalibration after the supply voltage and
temperature have stabilized may result in termination
resistances closer to the desired 50
Ω.
ISL54105A
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