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參數(shù)資料
| 型號： | ISL54222AIRUEVAL1Z |
| 廠商： | Intersil |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 1 FOR ISL54222AIRU |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
6
FN6902.1
February 4, 2010
Positive Supply Current, IDD VDD = 1.8V, SEL = 0V, OE = 0V
25
-
5.8
7.8
A
Full
-
-
8.3
A
Positive Supply Current, IDD
(Low Power State)
VDD = 1.8V, SEL = 0V, OE = VDD
25
-
0.12
0.3
A
Full
-
-
1
A
DIGITAL INPUT CHARACTERISTICS
Input Voltage Low, VSELL,
VOEL
VDD = 1.8V to 3.3V
Full
-
-
0.5
V
Input Voltage High, VSELH,
VOEH
VDD = 1.8V to 3.3V
Full
1.4
-
VDD
V
Input Current, ISELL, IOEL
VDD = 3.3V, SEL = 0V, OE = 0V
Full
-
170
-
nA
Input Current, ISELH
VDD = 3.3V, SEL = 3.3V
Full
-
-1.4
-
nA
Input Current, IOEH
VDD = 3.3V, OE = 3.3V
Full
-
-1.4
-
nA
NOTES:
11. VLOGIC = Input voltage to perform proper function.
12. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this
data sheet.
13. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established
by characterization and are not production tested.
14. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal
range.
15. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel
with lowest max rON value, between HSD2+ and HSD2- or between HSD1+ and HSD1-.
16. Limits established by characterization and are not production tested.
Electrical Specifications - 1.8V to 3.3V Supply
Test Conditions: VDD = +3.3V, GND = 0V, VSELH = 1.4V, VSELL = 0.5V,
VOEH =1.4V, VOEL = 0.5V, (Note 11), Unless Otherwise Specified.
Boldface limits apply over the operating temperature range,
-40°C to +85°C. (Continued)
PARAMETER
TEST CONDITIONS
TEMP
(°C)
MIN
(Notes 12, 13) TYP
MAX
(Notes 12, 13) UNITS
Test Circuits and Waveforms
Logic input waveform is inverted for switches that have the
opposite logic sense.
FIGURE 1A. MEASUREMENT POINTS
Repeat test for all switches. CL includes fixture and stray
capacitance.
FIGURE 1B. TEST CIRCUIT
FIGURE 1. SWITCHING TIMES
50%
tr < 20ns
tf < 20ns
tOFF
90%
VDD
0V
VINPUT
0V
tON
LOGIC
INPUT
SWITCH
INPUT
SWITCH
OUTPUT
90%
VOUT
V
OUT
V
(INPUT)
R
L
R
L
r
ON
+
------------------------
=
SWITCH
INPUT
VIN
VOUT
RL
CL
Dx
HSDxx
SEL
500
Ω
50pF
GND
VDD
C
OE
VINPUT
ISL54222A
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