FN7627.0 July 2, 2010 FIGURE 4. CAPACITANCE TEST CIRCUIT FIGURE 5. CROSSTALK TEST CIRCUIT FIGURE 6A. MEASUREMENT POINTS FIGURE 6B. TEST CIRCUIT " />
參數(shù)資料
型號: ISL54225IRTZEVAL1Z
廠商: Intersil
文件頁數(shù): 17/18頁
文件大小: 0K
描述: BOARD EVAL FOR ISL5425A MUX
標(biāo)準(zhǔn)包裝: 1
主要目的: 接口,USB 2.0 開關(guān)
嵌入式:
已用 IC / 零件: ISL54225
主要屬性: 2 通道
次要屬性: 2.7 V ~ 5.25 V 電源
已供物品:
8
FN7627.0
July 2, 2010
FIGURE 4. CAPACITANCE TEST CIRCUIT
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 6A. MEASUREMENT POINTS
FIGURE 6B. TEST CIRCUIT
FIGURE 6. SKEW TEST
Test Circuits and Waveforms (Continued)
VDD
C
GND
HSDxx
Dx
SEL
IMPEDANCE
ANALYZER
0V OR
Repeat test for all switches.
OE
VDD
ANALYZER
VDD
C
HSD1x
SIGNAL
GENERATOR
RL
GND
SEL
Dx
50
Ω
NC
Dx
HSD2x
Signal direction through switch is reversed, worst case values
are recorded. Repeat test for all switches.
OE
VIN
DIN+
DIN-
OUT+
OUT-
50%
90%
10%
90%
50%
90%
50%
tri
tfi
tro
tf0
tskew_i
tskew_o
OUT+
CL
COMD1
D2
GND
VDD
C
D1
COMD2
CL
OUT-
DIN+
DIN-
|tro - tri| Delay Due to Switch for Rising Input and Rising Output Signals.
|tfo - tfi| Delay Due to Switch for Falling Input and Falling Output Signals.
|tskew_0| Change in Skew through the Switch for Output Signals.
|tskew_i| Change in Skew through the Switch for Input Signals.
15.8
Ω
15.8
Ω
143
Ω
143
Ω
45
Ω
45
Ω
SEL
VIN
OE
ISL54225
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