10 FN7628.0 July 29, 2010 distortion and meet all the USB requirements for USB 2.0 full-speed signaling. See Figure 15 in the “Typical" />
參數(shù)資料
型號: ISL54228IRUZ-T
廠商: Intersil
文件頁數(shù): 2/17頁
文件大?。?/td> 0K
描述: IC USB SWITCH DPST OVP 8TQFN
標準包裝: 3,000
功能: 開關(guān)
電路: 2 x SPST
導通狀態(tài)電阻: 17 歐姆
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 2.7 V ~ 5.25 V
電流 - 電源: 45µA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 8-XFQFN
供應商設(shè)備封裝: 8-UTQFN(1.2x1.4)
包裝: 帶卷 (TR)
ISL54228
10
FN7628.0
July 29, 2010
distortion and meet all the USB requirements for USB
2.0 full-speed signaling. See Figure 15 in the “Typical
Performance Curves” on page 14 for USB Full-speed
Eye Pattern taken with switch in the signal path.
The switches are active (turned ON) whenever the OE
voltage is logic “1” (High) and the LP voltage is logic
“X” (Don’t Care) and OFF when the OE voltage is logic
“0” (Low) and the LP voltage is logic “X” (Don’t Care).
When the OE voltage is logic “0” (Low) and the LP
voltage is logic “1” (High) the part goes into low power
mode.
OVERVOLTAGE PROTECTION (OVP)
The maximum normal operating signal range for the Dx
switches is from 0V to 3.6V. For normal operation, the
signal voltage should not be allowed to exceed these
voltage levels or go below ground by more than -0.3V.
However, in the event that a positive voltage >3.8V
(typ) to 5.25V, such as the USB 5V VBUS voltage, gets
shorted to one or both of the COM+ and COM- pins or
a negative voltage < -0.45V (typ) to -5V gets shorted
to one or both of the COM pins, the ISL54228 has OVP
circuitry to detect the overvoltage condition and open
the SPST switches to prevent damage to the USB
down-stream transceiver connected at the signal pins
(D-, D+).
The OVP and power-off protection circuitry allows the
COM pins (COM-, COM+) to be driven up to 5.25V
while the VDD supply voltage is in the range of 0V to
5.25V. In this condition, the part draws < 100A of
ICOMx and IDD current and causes no stress to the IC.
In addition, the SPST switches are OFF and the fault
voltage is isolated from the other side of the switch.
External VDD Series Resistor to Limit IDD
Current During Negative OVP Condition
A 100Ω to 1kΩ resistor in series with the VDD pin (see
Figure 6) is required to limit the IDD current draw from
the system power supply rail during a negative OVP
fault event.
With a negative -5V fault voltage at both COM pins, the
graph in Figure 7 shows the IDD current draw for
different external resistor values for supply voltages of
5.25V, 3.6V, and 2.7V. Note: With a 500Ω resistor, the
current draw is limited to around 5mA. When the
negative fault voltage is removed, the IDD current will
return to it’s normal operation current of 25A to 45A.
The series resistor also provides improved ESD and
latch-up immunity. During an overvoltage transient
event (such as occurs during system level IEC 61000
ESD testing), substrate currents can be generated in
the IC that can trigger parasitic SCR structures to
turn ON, creating a low impedance path from the
VDD power supply to ground. This will result in a
significant amount of current flow in the IC, which
can potentially create a latch-up state or
permanently damage the IC. The external VDD
resistor limits the current during this over-stress
situation and has been found to prevent latch-up or
destructive damage for many overvoltage transient
events.
Under normal operation, the low microamp IDD
current of the IC produces an insignificant voltage
drop across the series resistor resulting in no impact
to switch operation or performance.
ISL54228 Operation
The following will discuss using the ISL54228 shown
POWER
The power supply connected at the VDD pin provides
the DC bias voltage required by the ISL54228 part for
proper operation. The ISL54228 can be operated with
a VDD voltage in the range of 2.7V to 5.25V.
For lowest power consumption you should use the
lowest VDD supply.
A 0.01F or 0.1F decoupling capacitor should be
connected from the VDD pin to ground to filter out
any power supply noise from entering the part. The
capacitor should be located as close to the VDD pin
as possible.
FIGURE 6. VDD SERIES RESISTOR TO LIMIT IDD
CURRENT DURING NEGATIVE OVP AND
FOR ENHANCED ESD AND LATCH-UP
IMMUNITY
FIGURE 7. NEGATIVE OVP IDD CURRENT vs
RESISTOR VALUE vs VSUPPLY
OE
D+
100Ω to 1kΩ
COM+
COM-
VSUPPLY
GND
C
PROTECTION
RESISTOR
OVP
LOGIC
D-
LP
IDD
VDD
-5V
FAULT
VOLTAGE
ALM
INT
LOW
TO
INDICATE
OVP
0
5
10
15
20
25
100 200 300 400 500 600 700 800 900 1k
RESISTOR (Ω)
I DD
(mA)
VCOM+ = VCOM- = -5V
2.7V
3.6V
5.25V
ISL54228
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