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參數資料
| 型號： | ISL55036EVAL1Z |
| 廠商： | Intersil |
| 文件頁數： | 2/11頁 |
| 文件大?。?/td> | 0K |
| 描述： | EVAL BOARD 1 FOR ISL55036 |
| 標準包裝： | 1 |
| 系列： | * |
10
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6640.1
September 11, 2008
degraded for traces greater than one inch, unless
controlled impedance (50
Ω or 75Ω) strip lines or
microstrips are used.
Match channel-to-channel analog I/O trace lengths and
layout symmetry. This will minimize propagation delay
mismatches.
Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e. no
split planes or PCB gaps under these lines). Avoid vias in the
signal I/O lines.
Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
When testing, use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
A minimum of 2 power supply decoupling capacitors are
recommended (1000pF, 0.01F) as close to the devices as
possible. Avoid vias between the capacitor and the device
because vias add unwanted inductance. Larger capacitors
can be farther away. When vias are required in a layout, they
should be routed as far away from the device as possible.
The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
The QFN Package Requires Additional PCB Layout
Rules for the Thermal Pad
The thermal pad is electrically connected to power supply
ground through the high resistance IC substrate. Its primary
function is to provide heat sinking for the IC. However,
because of the connection to the power ground pins through
the substrate, the thermal pad must be tied to the power
supply ground to prevent unwanted current flow through the
thermal pad. Maximum AC performance is achieved if the
thermal pad has good contact to the IC ground pins. Heat
sinking requirements can be satisfied using thermal vias
directly beneath the thermal pad to a heat dissipating layer
of a square at least 1” on a side.
FIGURE 26. BASIC APPLICATION CIRCUIT
V+(1,2,3)
EN(1,2,3)
V+_OUT(1,2,3)
OUT_2
IN+_5
IN+_2
IN+_3
GND_IN(1,2,3)
EN(4,5,6)
V+ (4,5,6)
IN+_4
OUT_3
GND_OUT(4,5,6)
GND_PWR(1,2,3)
OUT_6
+
-
+
-
+
-
DIE 1
+
-
+
-
+
-
DIE 2
IN+_1
IN+_6
OUT_1
GND_OUT(4,5,6)
V+_OUT(4,5,6)
OUT_5
OUT_4
GND_PWR(4,5,6)
GND_IN(4,5,6)
ROUT 1
ROUT 2
ROUT 3
ROUT 4
ROUT 5
ROUT 6
RIN 4
RIN 6
RIN 5
RIN 4
RIN 6
RIN 5
DECOUPLING
CAPACITORS
DECOUPLING
CAPACITORS
ISL55036
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