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參數(shù)資料
| 型號： | ISL5586DIMZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SLIC RINGING LP HOME 28-PLCC |
| 標(biāo)準(zhǔn)包裝： | 37 |
| 系列： | RSLIC18 |
| 功能： | 用戶線路接口概念（SLIC） |
| 電路數(shù)： | 1 |
| 電源電壓： | 5V |
| 電流 - 電源： | 5mA |
| 功率（瓦特）： | 305mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 28-PLCC（11.51x11.51） |
| 包裝： | 管件 |
| 包括： | 回路啟動和振鈴?fù)禉z測器，振鈴發(fā)生器，熱保護(hù) |
14
FN4924.2
November 3, 2004
Impedance and Gain Derivations
The feedback mechanism for monitoring the AC portion of
the loop current consists of two amplifiers, the sense
amplifier (SA) and the transmit amplifier (TA). The AC
feedback signal is used for impedance synthesis. A detailed
model of the AC feed back loop is provided below
Impedance Programming Resistor Derivation
The gain of the transmit amplifier, set by RS, determines the
programmed resistance of the SLIC. For complex line
terminations RS is replaced with a complex network ZS
(Figure 1). The capacitor CFB blocks the DC component of
the loop current. Figure 11 illustrates the impedance
synthesis loop. Note that the ground symbols shown in
Figures 11 through 14 represent AC grounds, not
necessarily actual DC potentials.
The receiver block provides a single-ended to differential
conversion with a voltage gain of 2. The voltage at Tip and
Ring due to the feedback from VZO is shown in Equation 35.
The Feedback amplifier (TA) provides the programmable
gain required for impedance synthesis to the Receiver block.
The output voltage (VZO) is a function of the Sense Amplifier
output voltage and the gain of the feedback amplifier, which
can be substituted for VZO.
The sense amplifier shown in Figure 11 is configured as a 4
input differential amplifier with a gain of 3/4. The output
voltage, VSA, is a function of the voltage across the Tip and
Ring sense resistors (20
each) which can also be
expressed in terms of loop current.
Substituting Equation 37 into Equation 35 and rearranging
terms yields Z0, the SLIC’s synthesized 2-wire impedance.
Rearranging and solving for RS, Equation 39 shows the
relationship between the impedance programming resistor
and the programmed impedance.
4-WIRE TO 2-WIRE GAIN
The 4-wire to 2-wire gain is defined as the gain from the
differential receive input to the 2-wire load ZL. The gain is a
function of the terminating impedance, synthesized
impedance and protection resistors and is illustrated in
Figure 12. The input current to the receiver block Irx4w
comes from the difference of the VRX input current and the
VZO feedback current. This current is fed to the Tip and Ring
amplifiers and yields the relationship shown in Equation 40.
The voltage VZO, is a function of the sense amplifier output
voltage VSA.
VSA can be expressed in terms of loop current as shown in
Equation 42.
Substituting Equation 42 into Equation 41 gives Equation 43.
The VZ0 term in Equation 40 can now be replaced by
Equation 43 yielding Equation 44.
A loop equation can be derived for the 2-wire side that
replaces VTR as shown in the equation below.
Expressing IL in terms of V2W/ZL, rearranging, and solving
for V2W yields the relationship between the 2-wire voltage
and the output of the Receive amplifier.
The differential voice input is configured for a gain of 1.4.
The relationship between VRX and the voice input is shown
in Equation 47. Substituting for VRX, the 4-2-Wire gain is
shown in Equation 48. Note that the differential voice input is
outside the impedance synthesis loop, so the gain of the
receive amplifier has no effect on the SLIC’s impedance.
When the combination of the device source impedance and
the protection resistors equal the terminating impedance, the
receive gain equals 2.92dB and is inverted with respect to
the 4-wire input.
2-WIRE TO 4-WIRE GAIN
The 2-wire to 4-wire gain (G24) is defined as the gain from the
Tip and Ring terminals (VTR) to the VTX differential output.
VTR
2
–
VZO
×
=
(EQ. 35)
VTR
2
–
VSA
×
RS
8K
------------
×
=
(EQ. 36)
VSA
220IL
3 4
)
(
×
–
=
(EQ. 37)
Z0
VTR
IL
-----------
420IL
3
4
---
×
Rs
8K
------------
×
60
Rs
8K
------------
×
==
=
(EQ. 38)
RS
133.3 Z0
×
=
(EQ. 39)
VTR
2Vrx VZO
–
()
×
–
=
(EQ. 40)
VZ0
VSA
RS
8K
------------
×
–
=
(EQ. 41)
VSA
IL220
3
4
---
×
–
=
(EQ. 42)
VZ0
IL220
3
4
---
×
RS
8K
------------
×
–
=
(EQ. 43)
VTR
2Vrx
×
–
2 IL220
3
4
---
×
RS
8K
------------
×
–
=
(EQ. 44)
V2W IL 2Rp
×
+
2Vrx
–
IL 4 20
3
4
---
×
RS
8K
------------
×
–
=
(EQ. 45)
V2W
2Vrx
ZL
ZL Z0 2RP
++
--------------------------------------
×
–
=
(EQ. 46)
Vrx
1.4
VRXP VRXM
–
()
×
1.4 VRX4W
×
==
(EQ. 47)
V2W
VRX4W
--------------------
2.8
ZL
ZO + 2RP + ZL
------------------------------------------
–
=
(EQ. 48)
ISL5586
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