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參數(shù)資料
| 型號： | ISL5729INZ |
| 廠商： | Intersil |
| 文件頁數(shù)： | 6/10頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAC 10BIT CMOS DUAL 48LQFP |
| 標準包裝： | 250 |
| 位數(shù)： | 10 |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 電壓電源： | 模擬和數(shù)字 |
| 功率耗散（最大）： | 274mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應商設備封裝： | 48-TQFP（7x7） |
| 包裝： | 托盤 |
| 輸出數(shù)目和類型： | * |
| 采樣率（每秒）： | 130M |
2011 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FT3001 Rev. 1.0.4
5
FT3001
—
Reset
Timer
with
Configurable
Delay
AC Electrical Characteristics
Unless otherwise specified, conditions of T
A
=-40 to 80°C with V
CC
=1.8 - 5.0 V OR TA=-25 to 85°C with VCC=1.7 – 5 V OR
T
A
=0 to 85°C with V
CC
=1.65 – 5 V produce the performance characteristics below.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Unit
tPHL1,
tPLH1
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=0)
CL=5 pF, RL=5 k,
Figure 9, Figure 4, Figure 5
2.40
3.00
3.60
s
Timer Delay, /SRn to /RST1
(DSR0=0, DSR1=1)
CL=5 pF, RL=5 k, Figure 9, Figure
4, Figure 5
3.00
3.75
4.50
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=0)
CL=5 pF, RL=10 k, Figure 6, Figure
7
3.60
4.50
5.40
Timer Delay, /SRn to RST2
(DSR0=1, DSR1=1),
CL=5 pF, RL=10 k, Figure 6, Figure
7
4.80
6.00
7.20
tREC
Reset Timeout Delay, /RST1 and
RST2
Figure 4, Figure 5, Figure 6, Figure 7
400
ms
Capacitance Specifications
TA = +25C.
Symbol
Parameter
Condition
Typical
Unit
CIN
Input Capacitance
VCC=GND
4.0
pF
COUT
Output capacitance
VCC=5.0 V
5.0
pF
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