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參數(shù)資料
| 型號(hào)： | ISL59119IBZ-T13 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 9/10頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DRVR TRI-CHN LPF 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 應(yīng)用： | 重構(gòu)濾波器 |
| 輸出類型： | 滿擺幅 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 8MHz |
| 轉(zhuǎn)換速率： | 25 V/µs |
| 電流 - 電源： | 9.5mA |
| 電流 - 輸出 / 通道： | 65mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
8
FN6319.2
August 25, 2008
Application Information
The ISL59119 is a single-supply rail-to-rail triple (one
S-video channel and one composite channel) video amplifier
with internal sync tip clamps, a typical -3dB bandwidth of
8MHz and slew rate of about 25V/s. This part is ideally
suited for applications requiring high composite and S-video
performance with very low power consumption. As the
performance characteristics and features illustrate, the
ISL59119 is optimized for portable video applications.
Internal Sync Clamp
Embedded video DACs typically use ground as their most
negative supply. This places the sync tip voltage at a
minimum of 0V. Presenting a 0V input to most single supply
amplifiers will saturate the output stage of the amplifier
resulting in a clipped sync tip and degraded video image.
The ISL59119 features an internal sync clamp and offset
function that level shifts the entire video signal to the
optimum level before it reaches the amplifiers’ input stage.
These features also help avoid saturation of the output stage
of the amplifier by setting the signal closer to the best
voltage range.
The simplified “Block Diagram” on page 1 shows the basic
operation of the ISL59119’s sync clamp. The Y and CVBS
inputs’ AC-coupled video sync signal is pulled negative by a
current source at the input. When the sync tip goes below
the comparator threshold, the comparator output goes high,
pulling up on the input through the diode, forcing current into
the coupling capacitor until the voltage at the input is again
0V, and the comparator turns off. This forces the sync tip
clamp to always be 0V, setting the offset for the entire video
signal. The C-Channel is slaved to the Y-Channel and
clamped to a 500mV level at the input.
Figure 27 shows the setup for testing the clamp’s response
to a large step response at the input.
Once the signals are clamped at the input they are level
shifted by +65mV before being amplified by a gain of x2.
Line Drift and DC Restore
The input coupling capacitor value is chosen from the
system requirements. A typical DC-restore application using
an NTSC video horizontal sync will result in a 60s hold time
(64s line time minus 4s sample time). The typical input
bias current to the video amplifier is 1A for the Y and CVBS
channels, so for a 60s hold time, and a 0.01F capacitor,
the output voltage drift is 6mV in one line. The restore
amplifier can provide a typical source current of 2.6mA to
charge the coupling capacitor, so with a 4s sampling time,
the output can be corrected by 1000mV in each line. The
drift on the chroma channel is less than 1mV per line.
Using a smaller value capacitors increases both the voltage
that can be corrected, as well as the droop while being held.
Likewise, using a larger value reduces the correction and
droop voltages. A sample of charging and droop rates are
shown in Table 1.
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT
TEMPERATURE
Typical Performance Curves
VDD = 3.3V, RL = 150Ω to GND, unless otherwise specified. (Continued)
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
PO
WER
D
ISS
IP
A
T
IO
N
(W)
0.4
1.0
0.8
0.2
0.6
0
100
125
150
50
25
75 85
435mW
909mW
θ
JA =
+23
0°C
/W
SO
T23
-6
θ
JA
=
+1
10
°C
/W
S
O
8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL
CONDUCTIVITY TEST BOARD
0
PO
WER
D
ISS
IP
A
T
IO
N
(W)
0.2
0.7
0.6
0.1
0.4
0.5
0.3
0
100
125
150
50
25
75 85
391mW
625mW
θ
JA
=
+1
60
°C
/W
S
O
8
θ
JA =
+2
56°
C/W
SO
T2
3-6
75
Ω
75
Ω
500
Ω
0.1F
NTSC VIDEO
1Hz SQUARE WAVE
150
Ω
OUTPUT
ISL59119
CH1
CH2
FIGURE 27. DC STEP RESPONSE CIRCUIT
ISL59119
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