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參數(shù)資料
| 型號： | ISL5927IN |
| 廠商： | INTERSIL CORP |
| 元件分類： | DAC |
| 英文描述： | Dual 14-Bit, +3.3V, 260+MSPS, High Speed D/A Converter |
| 中文描述： | DUAL, PARALLEL, WORD INPUT LOADING, 12-BIT DAC, PQFP48 |
| 封裝： | 7 X 7 MM, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 12/13頁 |
| 文件大?。?/td> | 675K |
| 代理商： | ISL5927IN |
12
theoretically improving the even order harmonic rejection,
but likely reducing the signal swing available due to the
output voltage compliance range limitations.
Propagation Delay
The converter requires two clock rising edges for data to be
represented at the output. Each rising edge of the clock
captures the present data word and outputs the previous
data. The propagation delay is therefore 1/CLK, plus <2ns of
processing. See Figure 15.
Test Service
Intersil offers customer-specific testing of converters with a
service called Testdrive. To submit a request, fill out the
Testdrive form at www.intersil.com/testdrive. Or, send a
request to the technical support center.
R
DIFF
ISL5927
R
LOAD
FIGURE 13. OUTPUT LOADING FOR DATASHEET
MEASUREMENTS
OUTA
OUTB
V
OUT
= (2 x OUTA x R
EQ
)V
1:1
LOAD SEEN BY THE TRANSFORMER
R
LOAD
REPRESENTS THE
R
EQ
= 0.5 x (R
LOAD
//R
DIFF
)
AT EACH OUTPUT
FIGURE 14. ALTERNATIVE OUTPUT LOADING
ISL5927
OUTA
OUTB
V
OUT
= (2 x OUTA x R
EQ
)V
R
EQ
= 0.5 x (R
LOAD
// R
DIFF
// R
A
), WHERE R
A
=R
B
AT EACH OUTPUT
R
LOAD
R
DIFF
R
A
R
B
LOAD SEEN BY THE TRANSFORMER
R
LOAD
REPRESENTS THE
Timing Diagram
FIGURE 15. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM
CLK
I
OUT
50%
t
PW1
t
PW2
t
SU
t
HLD
t
SU
t
SU
t
PD
t
HLD
t
HLD
D13-D0
W
0
W
1
W
2
W
3
OUTPUT=W
0
OUTPUT=W
1
t
PD
OUTPUT=W
-1
ISL5927
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