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參數(shù)資料
| 型號(hào)： | ISL59420IUZ-T7 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 3/13頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC AMP MULTIPLEX 400MHZ 10-MSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 2:1 多路復(fù)用器-放大器 |
| 電路數(shù)： | 1 |
| -3db帶寬： | 420MHz |
| 轉(zhuǎn)換速率： | 1462 V/µs |
| 電流 - 電源： | 11mA |
| 電流 - 輸出 / 通道： | 130mA |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 10-MSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 產(chǎn)品目錄頁(yè)面： | 1235 (CN2011-ZH PDF) |
| 其它名稱： | ISL59420IUZ-T7DKR |
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ISL59420
11
FN7459.2
July 3, 2012
Limiting the Output Current
No output short circuit current limit exists on this part. All
applications need to limit the output current to less than 50mA.
Adequate thermal heat sinking of the parts is also required.
PC Board Layout
The frequency response of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
The use of low inductance components such as chip resistors
and chip capacitors is strongly recommended.
Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the signal
lines add inductance at high frequency and should be avoided.
PCB traces greater than 1" begin to exhibit transmission line
characteristics with signal rise/fall times of 1ns or less. High
frequency performance may be degraded for traces greater
than one inch, unless strip lines are used.
Match channel-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
Maximize use of AC de-coupled PCB layers. All signal I/O lines
should be routed over continuous ground planes (i.e. no split
planes or PCB gaps under these lines). Avoid vias in the signal
I/O lines.
Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01F) as close to the device as
possible. Avoid vias between the cap and the device because
vias add unwanted inductance. Larger caps can be farther
away. When vias are required in a layout, they should be routed
as far away from the device as possible.
V+
V-
V+
V-
V+
V-
LOGIC
CONTROL
GND
IN0
IN1
S0
OUT
EXTERNAL
CIRCUITS
SCHOTTKY
PROTECTION
V+
V-
POWER
GND
SIGNAL
LOGIC
V+ SUPPLY
V- SUPPLY
DE-COUPLING
CAPS
FIGURE 27. SCHOTTKY PROTECTION CIRCUIT
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