參數(shù)資料
型號(hào)： ISL59483EVAL1Z
廠商： Intersil
文件頁(yè)數(shù)： 8/17頁(yè)
文件大?。?/td> 0K
描述： EVAL BOARD 1 FOR ISL59483
標(biāo)準(zhǔn)包裝： 1
系列： *
16
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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FN6394.2
May 21, 2007
4:1 RGB Dual Gain Video MUX
Connecting the MUX inputs and outputs in parallel allows the
8 channel ISL59483 to be used as a 4:1 RGB MUX with
selectable gains of 1 or 2 (Figure 10). In this example, the high
input impedance of the MUX enables each input video line to
be shared by any number of MUX input pins. The gain select
logic function is created by providing complememtary logic to
the HIZ1 and HIZ2 pins. Channels CH0 through CH3 are
selected by connecting the MUX 1 and MUX 2 S0-1, 2 and
S1-1, 2 channel select inputs together to form channel select
(S0 and S1), as shown in the truth table in Figure 10.
FIGURE 45. APPLICATION CIRCUIT FOR DUAL GAIN 4:1 VIDEO MUX
S1
GAIN
SELECT
GAIN
OUTA, B, C
00
0
1
CH0A, B, C
00
0
1
CH1A, B, C
11
0
1
CH2A, B, C
11
0
1
CH3A, B, C
00
1
2
CH0A, B, C
00
1
2
CH1A, B, C
11
1
2
CH2A, B, C
11
1
2
CH3A, B, C
+2
+1
ISL59483
1/3 MUX-AMP1
1/3 MUX-AMP2
OUTA1
IN0A1
OUTA2
IN1A2
IN1A1
IN2A1
IN3A1
IN0A2
IN2A2
IN3A2
S0-1
S1-1
HIZ1
S0-2
S1-2
HIZ2
CH0 - CH3
CHANNEL SELECT
CHANNELS B & C
NOT SHOWN
AND GAIN SELECT
S0
S1
CH0
CH1
CH2
CH3
CHANNEL SELECT TRUTH TABLE
DUAL GAIN 4:1 VIDEO MUX
CONTROL
LOGIC
OUT
GAIN
* ROUTA1
* ROUTA2
LOGIC INPUTS
* OPTIONAL - DEPENDING ON PARASITIC CAPACITANCE
SELECT
CONTROL
LOGIC
ISL59483
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