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參數(shù)資料
| 型號(hào)： | ISL59830IAZ-T7 |
| 廠商： | Intersil |
| 文件頁數(shù)： | 3/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC VIDEO DRIVER TRUE SGL 16-QSOP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 應(yīng)用： | 驅(qū)動(dòng)器 |
| 輸出類型： | 滿擺幅 |
| 電路數(shù)： | 3 |
| -3db帶寬： | 200MHz |
| 轉(zhuǎn)換速率： | 500 V/µs |
| 電流 - 電源： | 120mA |
| 電流 - 輸出 / 通道： | 50mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 剪切帶 (CT) |
| 其它名稱： | ISL59830IAZ-T7CT |
11
FN7489.6
May 4, 2006
exponentially modulated by the magnitude of the open loop
gain, output impedance increases with frequency as the
open loop gain decreases with frequency. This inductive-like
effect of the output impedance is countered in the ISL59830
with proprietary output stage topology, keeping the output
impedance low over a wide frequency range and making it
possible to easily and effectively drive relatively heavy
capacitive loads.(See Figure 11).
The Charge Pump
The ISL59830 charge pump provides a bottom rail up to
1.65V below ground while operating on a 0V to 3.3V power
supply. The charge pump is internally regulated to one-half
the potential of the positive supply. This internal multi-phase
charge pump is driven by a 160MHz differential ring
oscillator driving a series of inverters and charge storage
circuitry. Each series inverter charges and places parallel
adjoining charge circuitry slightly out of phase with the
immediately preceding block. The overall effect is sequential
discharge and generation of a very low ripple of about 10mV
that is applied to the amplifiers providing a negative rail of up
to -1.65V.
There are two options to reduce the output supply noise.
Add a 120
Ω bead in series between VCC and DVCC to
further reduce ripple.
Add a 20pF capacitor between the back load 75
Ω resistor
and ground (see the ISL59830A + DC-Restore Solution
schematic on page 10).
The system operates at sufficiently high frequencies that any
related charge pump noise is far beyond standard video
bandwidth requirements. Still, appropriate bypassing
discipline must be observed, and all pins related to either the
power supply or the charge pump must be properly
bypassed. See "Power Supply Bypassing and Printed Circuit
Board Layout" in this section.
To maximize resistance to latch-up, a diode should be added
between the VEEOUT pin (anode) and GND (cathode), as
shown in the Demo Board Schematic. This prevents VEE
from rising more than 0.7V above ground during startup.
(VEE > 1V above GND can cause latchup under some
conditions.)
IN+
IN-
BIAS
OUT
FIGURE 27.
VO
L
T
S
(10m
V/
DIV
)
TIME (20ns/DIV)
FIGURE 28. CHARGE PUMP OSCILLATION (AMP OUTPUT)
ISL59830
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