5 FN7548.0 September 2, 2011 BWCM Common Mode Amplifier Bandwidth 10k || 5pF load 24 MH" />
參數(shù)資料
型號(hào)： ISL59911IRZ
廠商： Intersil
文件頁(yè)數(shù)： 13/17頁(yè)
文件大?。?/td> 0K
描述： IC RCVR/EQUALZR TRPL DIFF 32QFN
標(biāo)準(zhǔn)包裝： 60
類型： 接收器
驅(qū)動(dòng)器/接收器數(shù)： 0/3
規(guī)程： 雙絞線
電源電壓： 5V
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 32-QFN 裸露焊盤(pán)（5x6）
包裝： 管件
ISL59911
5
FN7548.0
September 2, 2011
BWCM
Common Mode Amplifier Bandwidth
10k || 5pF load
24
MHz
SRCM
Common Mode Slew Rate
VIN = -0.5V to +1.5V
0.1
V/ns
INPUT CHARACTERISTICS
CMIR
Common-mode Input Range
Differential signal passed undistorted.
Effective headroom is reduced by the p-p
amplitude of differential swing divided by 2.
-3.2/+4.0
V
CMRR
Common-mode Rejection Ratio
Measured at 100kHz
88
dB
Measured at 10MHz
58
dB
CINDIFF
Differential Input Capacitance
Capacitance between VINP and VINM
0.5
pF
RINDIFF
Differential Input Resistance
Resistance between VIN+ and VIN-
(due to common mode input resistance)
20
k
Ω
CINCM
CM Input Capacitance
Capacitance from VIN+ and VIN- to GND
1.3
pF
RINCM
CM Input Resistance
Resistance from VIN+ and VIN- to GND
25
k
Ω
VINDIFF_P-P
Max P-P Differential Input Range
Delta VIN+ - VIN- when slope gain falls to 0.9
1.9
V
OUTPUT CHARACTERISTICS
VOUT
Output Voltage Swing
±2.75
V
IOUT
Output Drive Current
RL = 10Ω, VIN+ - VIN- = ±2V
±22
mA
V(VOUT)OS
Output Offset Voltage
Post-offset calibration
-20
-8
+5
mV
R(VCM)
CM Output Resistance of VCM_R/G/B
(CM Output Mode)
At 100kHz
2.5
Ω
Gain
x1 mode
x2 mode
0.95
1.9
1.0
2.0
1.05
2.1
V/V
ΔGain
Channel-to-Channel Gain Mismatch
x1 and x2 modes
±3
%
ONOISE
Integrated Noise at Output
Inputs @ GND through 50
Ω.
0m of Equalization (Nominal)
300m of Equalization
4
20
mVRMS
SYNCOUTHI
High Level output on VS/HSOUT
10k || 5pF load, SYNC Output Mode
V+ - 1.5
V
SYNCOUTLO
Low Level output on VS/HSOUT
10k || 5pF load, SYNC Output Mode
0.4
V
SCL, SDA PINS
fMAX
Maximum I2C Operating Frequency
400
kHz
VOL
SDA Output Low Level
VSINK = 6mA
0.4
V
VIH
Input High Level
3V
VIL
Input Low Level
1.5
V
VHYST
Input Hysteresis
0.55
V
ILEAKAGE
Input Leakage Current
±1
A
tGLITCH
Maximum Width of Glitch on SCL (or
SDA) Guaranteed to be Rejected
50
ns
ENABLE, ADDR0, ADDR1 PINS
VIH
Input High Level
3V
VIL
Input Low Level
0.8
V
ILEAKAGE
Input Leakage Current
±1
A
NOTE:
7. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Electrical Specifications V+ = V+R = V+G = V+B = +5V, V- = V-R = V-G = V-B = V-D = -5V, TA = +25°C, all registers at default settings
(equalizer stages set to minimum boost, noise filter set to max bandwidth, x2 gain mode, GAINDC = 0dB), all analog inputs at 0V, auto offset
calibration executed, RL = 5pF || (75Ω + 75Ω) to GND, thermal pad connected to -5V, unless otherwise specified. (Continued)
PARAMETER
DESCRIPTION
CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7)
UNIT
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