參數(shù)資料
型號(hào)： ISL59923IRZ-T7
廠商： Intersil
文件頁(yè)數(shù)： 4/16頁(yè)
文件大小： 0K
描述： IC ANLG VID LINE TRPL 20-QFN
標(biāo)準(zhǔn)包裝： 1,000
類型： 視頻延遲線
應(yīng)用： RGB 視頻信號(hào)
安裝類型： 表面貼裝
封裝/外殼： 20-VQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 20-QFN 裸露焊盤（5x5）
包裝： 帶卷 (TR)
12
FN6826.2
August 31, 2010
Figure 32 shows the ISL5992x block diagram. The 3 analog
inputs are ground referenced single-ended signals. After the
signal is received, the delay is introduced by switching filter
blocks into the signal path. Each filter block is an all-pass
filter introducing either 1, 1.5 or 2ns of delay. In addition to
adding delay, each filter block also introduces some low
pass filtering. As a result, the bandwidth of the signal path
decreases from the 0ns delay setting to the maximum delay
setting, as shown in Figures 2 through 9 of the “Typical
Performance Curves”.
In operation, it is best to allocate the most delayed signal
0ns delay then increase the delay on the other channels to
bring them into line. This will result in delay compensation
with the lowest power and distortion.
Serial Bus Operation
The ISL5992x is programmed via 8-bit words sent through
its serial interface. The first bit (MSB) of SDATA is latched on
the first falling clock edge after SENABLE goes low, as
shown in Figure 33. This bit should be a 0 under all
conditions. The next two bits determine the color register to
be written to: 01 = R, 02 = G, and 03 = B (00 is reserved for
the test register). The final five bits set the delay for the
specified color. After 8 bits are latched, any additional clocks
are treated as a new word (data is shifted directly to the final
registers as it is clocked in). This allows the user to write (for
example) the 24 bits of data necessary for R, G, and B as a
single 24-bit word. It is the user's responsibility to send
complete multiples of 8 clock cycles. The serial state
machine is reset on the falling edge of SENABLE, so any
data corruption that may have occurred due to too many or
too few clocks can be corrected with a new word with the
correct number of clocks. The initial value of all registers on
power-up is 0.
SENABLE
SCLOCK
SDATA
A1
A0
D4
D3
D2
D1
D0*
0
a
b
v
w
x
y
z
FIGURE 33. SERIAL TIMING
*D0 is 0 when addressing the test register
tSEN_SETUP
tSEN_CYCLE
TABLE 2. SERIAL BUS DATA
vwxyz
ISL59920
DELAY
ISL59921
DELAY
ISL59922
DELAY
ISL59923
DELAY
00000
0
00001
2
1.5
1
2
00010
4
3
2
4
00011
6
4.5
3
6
00100
8
6
4
8
00101
10
7.5
5
10
00110
12
9
6
12
00111
14
10.5
7
14
01000
16
12
8
16
01001
18
13.5
9
18
01010
20
15
10
20
01011
22
16.5
11
22
01100
24
18
12
24
01101
26
19.5
13
26
01110
28
21
14
28
01111
30
22.5
15
30
10000
32
24
16
N/A
10001
34
25.5
17
N/A
10010
36
27
18
N/A
10011
38
28.5
19
N/A
10100
40
30
20
N/A
10101
42
31.5
21
N/A
10110
44
33
22
N/A
10111
46
34.5
23
N/A
11000
48
36
24
N/A
11001
50
37.5
25
N/A
11010
52
39
26
N/A
11011
54
40.5
27
N/A
11100
56
42
28
N/A
11101
58
43.5
29
N/A
11110
60
45
30
N/A
11111
62
46.5
31
N/A
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01;
Green register - ab = 10; Blue register - ab = 11; vwxyz selects
delay; ab = 00 writes to the test register to change the DAC slice
level.
TABLE 2. SERIAL BUS DATA (Continued)
vwxyz
ISL59920
DELAY
ISL59921
DELAY
ISL59922
DELAY
ISL59923
DELAY
ISL59920, ISL59921, ISL59922, ISL59923
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