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參數(shù)資料
| 型號： | ISL6123 |
| 廠商： | Intersil Corporation |
| 英文描述： | Octal Transparent D-Type Latches With 3-State Outputs 20-TSSOP -40 to 85 |
| 中文描述： | 電源順序控制器 |
| 文件頁數(shù)： | 8/16頁 |
| 文件大小： | 422K |
| 代理商： | ISL6123 |
8
Using the ISL612XSEQEVAL1 Platform
The
ISL612XSEQEVAL1
platform is the primary evaluation
board for this family. The board has 2 complete, separate
and electrically identical circuits, see Figure 15 for schematic
and Figure 16 for a photo.
In the top right hand corner of the board is a SMD layout with
a
ISL6123
illustrating the full functionality and small
implementation size for an application having the highest
component count.
The majority of the board is given over to a socket and
discrete through-hole components circuit for ease of
evaluation flexibility through IC variant swapping and
modification of UVLO levels and sequencing order by
passive component substitution.
The board is shipped with the
ISL6123
installed in both
locations and with two each of the other released variant
types loose packed. As this sequencer family has a common
function pinout there are no major modifications to the board
necessary to evaluate the other ICs. The
ISL6125
due to its
having open drain outputs can be evaluated on the
ISL612XSEQEVAL1
with a minor modification or on the
ISL613XSUPEREVAL2
evaluation platform. To modify for
ISL6125
evaluation, pull-up resistors must be added from
the GATE outputs to a pull-up voltage of 1.5V to prevent
FET turn-on or remove FETs to eliminate this voltage
restriction.
To the left, right and above the socket are four test point
strips (TP1-TP4). These give access to the labeled IC I/O
pins during evaluation. Remember that significant current or
capacitive loading of particular I/O pins will affect
functionality and performance.
Attention to orientation and placement of variant ICs in the
socket must be paid to prevent IC damage or faulty
evaluation.
Typical Performance Curves
FIGURE 4. UVLO THRESHOLD VOLTAGE
FIGURE 5. DLY CHARGE CURRENT
FIGURE 6. SYSRST# LOW TO OUTPUT LATCH OFF
634
633
632
631
628
626
U
TEMPERATURE (
o
C)
627
-40
0
20
60
-20
40
80
100
630
629
V
DD
= 5V
V
DD
= 1.5V
D
-40
0
20
60
-20
40
80
100
TEMPERATURE (
o
C)
1.03
1.02
0.97
0.98
0.99
1.00
1.01
1.04
DLY_OFF/ON
V
DD
= +5V
V
DD
= 1.5V
1
μ
s/DIV
5VOUT
GATE
SYSRST#
2V/DIV
3.3VOUT
ISL6123, ISL6124, ISL6125, ISL6126, ISL6127, ISL6128
相關PDF資料 |
PDF描述 |
|---|---|
| ISL6124 | Power Sequencing Controllers |
| ISL6125 | Power Sequencing Controllers |
| ISL6126 | Power Sequencing Controllers |
| ISL6127 | Power Sequencing Controllers |
| ISL6128 | Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs 20-SOIC -40 to 85 |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6123_07 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Sequencing Controllers |
| ISL6123_11 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Power Sequencing Controllers |
| ISL6123IR | 功能描述:IC POWER SUPPLY SEQUENCER 24QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6123IR-T | 功能描述:IC CTRLR PWR SEQUENCE 4CH 24-QFN RoHS:否 類別:集成電路 (IC) >> PMIC - 電源控制器，監(jiān)視器 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:- 應用:多相控制器 輸入電壓:- 電源電壓:9 V ~ 14 V 電流 - 電源:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應商設備封裝:40-TQFN-EP（5x5） 包裝:帶卷 (TR) |
| ISL6123IRZA | 功能描述:監(jiān)控電路 W/ANNEAL LV 4-CH PWR SEQUENCE-ENABLEHI RoHS:否 制造商:STMicroelectronics 監(jiān)測電壓數(shù): 監(jiān)測電壓: 欠電壓閾值: 過電壓閾值: 輸出類型:Active Low, Open Drain 人工復位:Resettable 監(jiān)視器:No Watchdog 電池備用開關:No Backup 上電復位延遲（典型值）:10 s 電源電壓-最大:5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:UDFN-6 封裝:Reel |
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