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參數(shù)資料
| 型號： | ISL6141CBZA |
| 廠商： | INTERSIL CORP |
| 元件分類： | 電源管理 |
| 英文描述： | Negative Voltage Hot Plug Controller |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | LEAD FREE, PLASTIC, MS-012AA, SOIC-8 |
| 文件頁數(shù)： | 16/19頁 |
| 文件大?。?/td> | 428K |
| 代理商： | ISL6141CBZA |
16
When any of the 4 conditions occur that turn off the GATE
(OV, UV, UVLO, Over-Current Time-Out) the PWRGD latch
is reset and the Q2 DMOS device will shut off (high
impedance). The pin will quickly be pulled high by the
external module (or an optional pull-up resistor or equivalent)
which in turn will disable it. If a pull-up resistor is used, it can
be connected to any supply voltage that doesn’t exceed the
IC pin maximum ratings on the high end, but is high enough
to give acceptable logic levels to whatever signal it is driving.
An external clamp may be used to limit the voltage range.
The PWRGD can also drive an opto-coupler (such as a
4N25), as shown in Figure 31
or LED (Figure 32). In both
cases, they are on (active) when power is good. Resistors
R12 or R13 are chosen, based on the supply voltage, and
the amount of current needed by the loads.
ISL6151
(H version; Figure 33): Under normal conditions
(DRAIN voltage - V
EE
< V
PG
, and
V
GATE
- V
GATE
< V
GH
),
the Q3 DMOS will be on, shorting the bottom of the internal
resistor to V
EE
, and turning Q2 off. If the pull-up current from
the external module is high enough, the voltage drop across
the 6.2k
resistor will look like a logic high (relative to
DRAIN). Note that the module is only referenced to DRAIN,
not V
EE
(but under normal conditions, the FET is on, and the
DRAIN and V
EE
are almost the same voltage).
When any of the 4 conditions occur that turn off the GATE,
the Q3 DMOS turns off, and the resistor and Q2 clamp the
PWRGD pin to one diode drop (~0.7V) above the DRAIN
pin. This should be able to pull low against the module pull-
up current, and disable the module.
Applications: GATE pin
To help protect the external FET, the output of the GATE pin
is internally clamped; up to an 80V supply and will not be any
higher than 15V. Under normal operation when the supply
voltage is above 20V, the GATE voltage will be regulated to a
nominal 13.6V above V
EE
.
Applications: “Brick” Regulators
One of the typical loads used are DC/DC regulators, some
commonly known as “brick” regulators, (partly due to their
shape, and because it can be considered a “building block”
of a system). For a given input voltage range, there are
usually whole families of different output voltages and
current ranges. There are also various standardized sizes
and pinouts, starting with the original “full” brick, and since
getting smaller (half-bricks and quarter-bricks are now
common).
Other common features may include: all components (except
some filter capacitors) are self-contained in a molded plastic
package; external pins for connections; and often an
ENABLE input pin to turn it on or off. A hot plug IC, such as
the ISL6141 is often used to gate power to a brick, as well as
turn it on.
Many bricks have both logic polarities available (Enable Hi or
Lo input); select the ISL6141 (L version) and ISL6151 (H
version) to match. There is little difference between them,
although the L version output is usually simpler to interface.
The Enable input often has a pull-up resistor or current
source, or equivalent built in; care must be taken in the
ISL6151 (H version) output that the given current will create
a high enough input voltage (remember that current through
the RPG 6.2k
resistor generates the high voltage level; see
Figure 33).
The input capacitance of the brick is chosen to match its
system requirements, such as filtering noise, and
maintaining regulation under varying loads. Note that this
input capacitance appears as the load capacitance of the
ISL6141/51.
OPTO
PWRGD
FIGURE 31. ACTIVE LOW ENABLE OPTO-ISOLATOR
R12
+
V
EE
V
PG
V
DD
Q2
(SECTION OF) ISL6141
(L VERSION)
-
+-
V
EE
GATE
V
GATE
PWRGD
DRAIN
+
-
+
LOGIC
+
LATCH
V
GH
LED (GREEN)
R13
FIGURE 32. ACTIVE LOW ENABLE WITH LED
+
V
EE
V
PG
V
DD
Q2
(SECTION OF) ISL6141
(L VERSION)
-
+-
V
EE
GATE
V
GATE
PWRGD
DRAIN
+
+
-
LOGIC
+
LATCH
V
GH
V
EE
PWRGD
DRAIN
VDD
+
VIN+
VIN-
ON/OFF
VOUT+
VOUT-
CL
Q3
Q2
RPG
6.2K
ACTIVE HIGH
ENABLE
MODULE
(SECTION OF) ISL6151
(H VERSION)
-
FIGURE 33. ACTIVE HIGH ENABLE MODULE
+
V
PG
+-
V
EE
GATE
V
GATE
+
-
+
LOGIC
+
LATCH
V
GH
ISL6141, ISL6151
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| ISL6141CBZA-T | 功能描述:IC CTRLR HOT PLUG NEG VOLT 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 類型:熱插拔開關(guān) 應(yīng)用:通用 內(nèi)部開關(guān):是 電流限制:可調(diào) 電源電壓:9 V ~ 13.2 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:管件 |
| ISL6141IB | 功能描述:IC CTRLR HOT PLUG NEG VOLT 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 類型:熱插拔開關(guān) 應(yīng)用:通用 內(nèi)部開關(guān):是 電流限制:可調(diào) 電源電壓:9 V ~ 13.2 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:管件 |
| ISL6141IB-T | 功能描述:IC CTRLR HOT PLUG NEG VOLT 8SOIC RoHS:否 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 類型:熱插拔開關(guān) 應(yīng)用:通用 內(nèi)部開關(guān):是 電流限制:可調(diào) 電源電壓:9 V ~ 13.2 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:管件 |
| ISL6141IBZA | 功能描述:IC CTRLR HOT PLUG NEG VOLT 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 類型:熱插拔開關(guān) 應(yīng)用:通用 內(nèi)部開關(guān):是 電流限制:可調(diào) 電源電壓:9 V ~ 13.2 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:管件 |
| ISL6141IBZA-T | 功能描述:IC CTRLR HOT PLUG NEG VOLT 8SOIC RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- 類型:熱插拔開關(guān) 應(yīng)用:通用 內(nèi)部開關(guān):是 電流限制:可調(diào) 電源電壓:9 V ~ 13.2 V 工作溫度:-40°C ~ 150°C 安裝類型:表面貼裝 封裝/外殼:10-WFDFN 裸露焊盤 供應(yīng)商設(shè)備封裝:10-TDFN-EP（3x3） 包裝:管件 |
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