參數(shù)資料
型號(hào)： ISL6225CA
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Octal D-Type Transparent Latches With 3-State Outputs 20-SSOP -40 to 85
中文描述： DUAL SWITCHING CONTROLLER, 345 kHz SWITCHING FREQ-MAX, PDSO28
封裝： PLASTIC, SSOP-28
文件頁(yè)數(shù)： 5/19頁(yè)
文件大?。?/td> 522K
代理商： ISL6225CA
5
FN9049.7
December 28, 2004
Functional Pin Description
GND (Pin 1)
Signal ground for the IC.
LGATE1, LGATE2 (Pin 2, 27)
These are outputs of the lower MOSFET drivers.
PGND1, PGND2 (Pin 3, 26)
These pins provide the return connection for lower gate
drivers. These pins are connected to sources of the lower
MOSFETs of their respective converters.
PHASE1, PHASE2 (Pin 4, 25)
The PHASE1 and PHASE2 points are the junction points of
the upper MOSFET sources, output filter inductors, and
lower MOSFET drains. Connect these pins to the respective
converter’s upper MOSFET source.
UGATE1, UGATE2 (Pin 5, 24)
These pins provide the gate drive for the upper MOSFETs.
BOOT1, BOOT2 (Pin 6, 23)
These pins power the upper MOSFET drivers of the PWM
converter. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode. Anode of
the bootstrap diode is connected to the VCC pin.
ISEN1, ISEN2 (Pin 7, 22)
These pins are used to monitor the voltage drop across the
lower MOSFET for current feedback and overcurrent
protection. For precise current detection these inputs can be
connected to the optional current sense resistors placed in
series with the source of the lower MOSFETs.
EN1, EN2 (Pin 8, 21)
These pins enable operation of the respective converter
when high. When both pins are low, the chip is disabled and
only low leakage current <1
μ
A is taken from V
CC
and V
IN
.
These pins are to be connected together and switched at the
same time.
VOUT1, VOUT2 (Pin 9, 20)
These pins when connected to the converters’ respective
outputs provide the output voltage inside the chip to reduce
output voltage excursion during HYS/PWM transition. When
connected to ground, these pins command forced
converters operate in continuous conduction mode at all
load levels.
VSEN1, VSEN2 (Pin 10, 19)
These pins are connected to the resistive dividers that set
the desired output voltage. The PGOOD, UVP, and OVP
circuits use this signal to report output voltage status.
OCSET1 (Pin 11)
A resistor from this pin to ground sets the overcurrent
threshold for the first controller.
SOFT1, SOFT2 (Pin 12, 17)
These pins provide soft-start function for their respective
controllers. When the chip is enabled, the regulated 5
μ
A
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SOFT pin.
DDR (Pin 13)
This pin, when high, transforms dual channel chip into
complete DDR memory solution. The OCSET2 pin becomes
an input to provide the required tracking function. The
channel synchronization is changed from out-of-phase to in-
phase. The PG2/REF pin becomes the output of the VDDQ/
2 buffered voltage that is used as a reference voltage by the
second channel.
VIN (Pin 14)
Provides battery voltage to the oscillator for feed-forward
rejection of the input voltage variation.
When connected to ground via 100k
resistor while the
DDR pin is high, this pin commands the out-of-phase 90
o
channels synchronization for reduced inter-channel
interference.
PG1 (Pin 15)
PGOOD1 is an open drain output used to indicate the status
of the output voltage. This pin is pulled low when the first
channel output is not within
±10% of the set value.
PG2/REF (Pin 16)
This pin has a double function depending on the mode the
chip is operating. When the chip is used as a dual channel
PWM controller (DDR = 0), the pin provides a PGOOD2
function for the second channel. The pin is pulled low when
the second channel output is not within
±10% of the set value.
In DDR mode (DDR = 1), this pin serves as an output of the
buffer amplifier that provides VDDQ/2 reference voltage
applied to the OCSET2 pin.
OCSET2 (Pin 18)
In a dual channel application (DDR = 0), a resistor from this
pin to ground sets the overcurrent threshold for the second
controller.
In the DDR application (DDR = 1), this pin sets the output
voltage of the buffer amplifier and the second controller and
should be connected to the center point of a divider from the
VDDQ output.
VCC (Pin 28)
This pin powers the controller.
ISL6225
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