參數(shù)資料
型號: ISL6244CRZ-T
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: Octal D-Type Transparent Latches With 3-State Outputs 20-SO -40 to 85
中文描述: SWITCHING CONTROLLER, 1000 kHz SWITCHING FREQ-MAX, PQCC32
封裝: 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHD-2, QFN-32
文件頁數(shù): 15/25頁
文件大?。?/td> 845K
代理商: ISL6244CRZ-T
15
FN9106.3
December 28, 2004
Second, the ISL6244 features an enable input (EN) for
power sequencing between the controller bias voltage and
another voltage rail. The enable comparator holds the
ISL6244 in shutdown until the voltage at EN rises above
1.23V. The enable comparator has about 90mV of hysteresis
to prevent bounce. It is important that the driver ICs reach
their POR level before the ISL6244 becomes enabled. The
schematic in Figure 20 demonstrates sequencing the
ISL6244 with the ISL620X family of Intersil MOSFET drivers
which require 5V bias.
The 11111 VID code is reserved as a signal to the controller
that no load is present. The controller will enter shutdown
mode after receiving this code and will start up upon
receiving any other code. This code is not intended as a
means of enabling the controller when a load is present.
To enable the controller, VCC must be greater than the POR
threshold; the voltage on EN must be greater than 1.23V;
and VID cannot be equal to 11111. Once these conditions
are true, the controller immediately initiates a soft-start
sequence.
Soft-Start
The soft-start time, t
SS
, is determined by an 11-bit counter
that increments with every pulse of the phase clock. For
example, a converter switching at 250kHz per phase has a
soft-start time of
During the soft-start interval, the soft-start voltage, V
RAMP
,
increases linearly from zero to 140% of the programmed
DAC voltage. At the same time a current source, I
RAMP
, is
decreasing from 160
μ
A down to zero. These signals are
connected as shown in Figure 21 (I
OUT
may or may not be
connected to FB depending on the particular application).
The ideal diodes in Figure 21 assure that the controller tries
to regulate its output to the lower of either the reference
voltage or V
RAMP
. Since I
RAMP
creates an initial offset
across R
FB
of (R
FB
x 160
μ
A), the first PWM pulse will not be
seen until V
RAMP
is greater than the R
FB
I
RAMP
offset. This
produces a delay after the ISL6244 enables before the
output voltage starts moving. For example, if VID = 1.5V,
R
FB
= 1k
and T
SS
= 8.3ms, the delay time can be
expressed using Equation 11.
Following the delay, the soft start ramps linearly until V
RAMP
reaches VID. For the system described above, this first
linear ramp will continue for approximately
The final portion of the soft-start sequence is the time
remaining after V
RAMP
reaches VID and before I
RAMP
gets to
zero. This is also characterized by a slight change in the slope
of the output voltage ramp which, for the current example,
exists for a time of
This behavior is seen in the example in Figure 22 of a
converter switching at 500kHz. For this converter, R
FB
is
set to 2.67k
leading to T
SS
= 4.0ms, t
DELAY
= 700ns,
t
RAMP1
= 2.23ms, and t
RAMP2
= 1.17ms.
FIGURE 20. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
-
+
1.23V (±2%)
EXTERNAL CIRCUIT
ISL6244 INTERNAL CIRCUIT
EN
+5V
VCC
+5V
POR
CIRCUIT
OV LATCH
SIGNAL
3.64k
1.40k
ENABLE
COMPARATOR
T
SS
SW
f
8.3ms
=
=
(EQ. 10)
FIGURE 21. RAMP CURRENT AND VOLTAGE FOR
REGULATING SOFT-START SLOPE
AND DURATION
-
+
I
AVG
REFERENCE
VOLTAGE
EXTERNAL CIRCUIT
ISL6244 INTERNAL CIRCUIT
COMP
C
C
R
C
R
FB
FB
IOUT
VDIFF
ERROR AMPLIFIER
V
COMP
V
RAMP
I
RAMP
IDEAL DIODES
t
DELAY
T
R
FB
160
1
10
6
×
--------1.4 VID
+
--------------------------------------------------
560
μ
s
=
=
(EQ. 11)
t
RAMP1
T
1.4
t
DELAY
=
5.27ms
=
(EQ. 12)
t
RAMP2
T
SS
t
RAMP1
t
DELAY
=
2.34ms
=
(EQ. 13)
ISL6244
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