參數(shù)資料
型號(hào)： ISL6251
廠商： Intersil Corporation
英文描述： Octal D-Type Transparent Latches With 3-State Outputs 20-TSSOP -40 to 85
中文描述： 低成本多化學(xué)電池充電器控制器
文件頁(yè)數(shù)： 17/20頁(yè)
文件大小： 593K
代理商： ISL6251
17
FN9202.1
June 17, 2005
The voltage gain with open current loop is:
Where
, V
FB
is the feedback voltage of the voltage
error amplifier. The Voltage loop gain with current loop
closed is given by:
If T
i
(S)>>1, then it can be simplified as follows:
,
From the above equation, it is shown that the system is a
single order system, which has a single pole located at
before the half switching frequency. Therefore, simple type II
compensator can be easily used to stabilize the system.
Figure 15 shows the voltage loop compensator, and its
transfer function is expressed as follows:
FIGURE 14. SMALL SIGNAL MODEL OF SYNCHRONOUS
BUCK REGULATOR
FIGURE 15. VOLTAGE LOOP COMPENSATOR
where
Compensator design goal:
High DC gain
Loop bandwidth f
c
:
Gain margin: >10dB
Phase margin: 40°
The compensator design procedure is as follows:
1. Put compensator zero at:
2. Put one compensator pole at zero frequency to achieve
high DC gain, and put another compensator pole at either
ESR zero frequency or half switching frequency,
whichever is lower.
The loop gain T
v
(S) at cross over frequency of f
c
has unity
gain. Therefore, the compensator resistance R
1
is
determined by:
where g
m
is the trans-conductance of the voltage loop error
amplifier. Compensator capacitor C1 is then given by:
Example: V
in
=19V, V
o
=16.8V, I
o
=2.6A, f
s
=300kHz,
C
o
=10
μ
F/10m
, L=10
μ
H, g
m
=250
μ
s, R
T
=0.2
, V
FB
=2.1V,
V
PWM
=V
IN
/11, f
c
=20kHz, then compensator resistance
R
1
=8.0k
. Choose R
1
=10k
. Put the compensator zero at
1.5kHz. The compensator capacitor is C
1
=10nF. Therefore,
choose voltage loop compensator: R
1
=10K, C
1
=10nF.
PCB Layout Considerations
Power and Signal Layers Placement on the PCB
As a general rule, power layers should be close together,
either on the top or bottom of the board, with signal layers on
the opposite side of the board. As an example, layer
arrangement on a 4-layer board is shown below:
1. Top Layer: signal lines, or half board for signal lines and
the other half board for power lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
Separate the power voltage and current flowing path from
the control and logic level signal path. The controller IC will
( )
S
( )
S
A
F
KF
)
S
(
T
v
1
m
v
=
o
FB
V
V
K
=
( )
( )
S
T
i
1
T
+
)
S
(
L
v
v
=
( )
( )
S
H
A
S
1
S
1
R
R
R
V
V
)
S
(
L
e
v
p
esr
T
L
o
o
FB
v
ω
ω
+
+
+
=
o
o
p
C
R
1
≈
ω
p
ω
d
V
in
d
I
L
in
v
L
+
1:D
+
Co
Rc
Ro
-Av(S)
d
comp
v
R
T
Fm
He(S)
+
T
i
(S)
K
o
v
T
v
(S)
in
i
L
i
-
+
R1
C1
V
REF
V
FB
Vo
g
m
V
COMP
( )
S
SC
S
1
g
v
v
A
1
cz
m
,
FB
comp
v
ω
+
=
1
=
C
R
1
1
cz
=
ω
s
f
20
1
5
1
(
1
)
o
o
cz
C
R
1
3
=
ω
FB
m
T
o
o
V
c
1
g
R
C
V
f
2
R
π
=
cz
1
R
1
ω
C
=
ISL6251, ISL6251A
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