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參數(shù)資料
| 型號： | ISL6269CRZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single Phase PWM Controller for Mobile Graphical Processing Unit (GPU) |
| 中文描述： | SWITCHING CONTROLLER, 600 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 4 X 4 MM, ROHS COMPLIANT, PLASTIC, MO-220-VGGC, QFN-16 |
| 文件頁數(shù)： | 14/17頁 |
| 文件大?。?/td> | 395K |
| 代理商： | ISL6269CRZ |
14
FN9177.0
June 14, 2005
assumed to be the conduction loss only and can be written
as:
]
2
r
DS ON
For the high-side MOSFET, its conduction loss can be
written as:
]
2
r
=
For the high-side MOSFET, its switching loss can be written
as:
V
I
T
F
2
The peak and valley current of the inductor can be obtained
based on the inductor peak-to-peak current and the load
current. The turn-on and turn-off time can be estimated with
the given gate driver parameters in the Electrical
Specification Table.
Selecting The Bootstrap Capacitor
The selection of the bootstrap capacitor can be written as:
Q
BOOT
Where:
- Q
g
is the total gate charge required to switch the high-
side MOSFET
-
V
BOOT
, is the maximum allowed voltage decay across
the boot capacitor each time the MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total
gate charge Q
G
, of 25nC at V
GS
= 5V, and a
V
BOOT
of
200mV. The calculated bootstrap capacitance is 0.125μF;
select at least the first standard component value of greater
capacitance than calculated, that being 0.15μF. Use an X7R
or X5R ceramic capacitor.
Layout Considerations
Power and Signal Layer Placement on the PCB
As a general rule, power layers should be adjacent to one
another towards one side of the board, with signal layers
adjacent to one another towards the opposite side of the
board. For example, prospective layer arrangement on a 4
layer board is shown below:
1. Top Layer: ISL6269 signal lines
2. Signal Ground
3. Power Layers: Power Ground
4. Bottom Layer: Power MOSFET, Inductors and other
Power traces
It is a good engineering practice to separate the power
conductors from the signal conductors. The controller IC will
stay on the signal layer, which is isolated by the signal
ground to the power signal traces. The loop formed by the
bottom MOSFET, output inductor, and output capacitor,
should be very small.
A guard-ring placed around high impedance inputs FB and
FSET is recommended.
Component Placement
Power MOSFETs should be placed close to the IC so that
VIN, LG, UG, PHASE, BOOT, and ISEN traces can be short.
Place components in such a way that the area near the
FSET, FB, COMP, and VO pins avoid traces with high dv/dt
and di/dt, such as gate signals and phase node signals.
Signal Ground and Power Ground Connection
The bottom of the ISL6269 QFN package is the analog and
logic ground terminal (GND) of the IC. Connect the GND pad
of the ISL6269 to the signal ground layer of the pcb using at
least five vias, for a robust thermal and electrical conduction
path. The best tie-point between the signal ground and the
power ground is at the negative side of the output capacitors
that is not in the return path of the inductor ripple current
flowing through the output capacitors.
Pin 1 (VIN)
The VIN pin should be connected to the drain of the high-
side MOSFET, using a low resistance and low inductance
path.
Pin 2 VCC
For best performance the LDO requires at least a 1μF MLCC
decouple capacitor connected from the VCC pin to the GND
pin.
Pin 3 (FCCM) and Pin 4 (EN)
These are logic inputs that are referenced to the GND pin.
Treat as a typical logic signal.
P
CONLS
D V
IN
)
I
LOAD
[
)
LS
1
D V
IN
)
–
[
]
≈
(EQ. 15)
P
CONHS
D V
IN
)
I
LOAD
[
DS ON
)
HS
D
V
IN
(
)
(EQ. 16)
P
SWHS
V
IN
(
)
------------------------------------------------------------
V
I
T
F
--------------------------------------------------------------------
2
+
=
(EQ. 17)
C
BOOT
-----------------------
=
(EQ. 18)
FIGURE 5. TYPICAL POWER COMPONENT PLACEMENT
V
IN
-
+
V
-
+
L
o
o
L
o
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ISL6269CRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6269EVAL2Z | 功能描述:EVALUATION BOARD FOR ISL6269 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - DC/DC 與 AC/DC（離線）SMPS 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開關(guān):3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6269IRZ | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6269IRZ-T | 功能描述:IC REG CTRLR BUCK PWM 16-QFN RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:Robust Ripple Regulator™ (R³) 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:275kHz 占空比:50% 電源電壓:18 V ~ 110 V 降壓:無 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:是 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 包裝:帶卷 (TR) |
| ISL6271A | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Integrated XScale Regulator |
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