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參數(shù)資料
| 型號： | ISL6405EEBZ |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Quadruple 2-Input Positive-NAND Gates 14-SSOP -40 to 85 |
| 中文描述： | SWITCHING CONTROLLER, 240 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | LEAD FREE, PLASTIC, SOIC-28 |
| 文件頁數(shù)： | 9/13頁 |
| 文件大?。?/td> | 341K |
| 代理商： | ISL6405EEBZ |
9
Byte Format
Every byte put on the SDA line must be eight bits long. The
number of bytes that can be transmitted per transfer is
unrestricted. Each byte has to be followed by an
acknowledge bit. Data is transferred with the most significant
bit first (MSB).
Acknowledge
The master (microprocessor) puts a resistive HIGH level on
the SDA line during the acknowledge clock pulse (Figure 3).
The peripheral that acknowledges has to pull down (LOW)
the SDA line during the acknowledge clock pulse, so that the
SDA line is stable LOW during this clock pulse. (Of course,
set-up and hold times must also be taken into account.)
The peripheral which has been addressed has to generate
an acknowledge after the reception of each byte, otherwise
the SDA line remains at the HIGH level during the ninth
clock pulse time. In this case, the master transmitter can
generate the STOP information in order to abort the transfer.
The ISL6405 will not generate the acknowledge if the
POWER OK signal from the UVLO is LOW.
Transmission Without Acknowledge
Avoiding detection of the acknowledgement, the
microprocessor can use a simpler transmission; it waits one
clock without checking the slave acknowledging, and sends
the new data.
This approach, though, is less protected from error and
decreases the noise immunity.
ISL6405 Software Description
Interface Protocol
The interface protocol is comprised of the following, as
shown below in Table 2:
A start condition (S)
A chip address byte (MSB on left; the LSB bit determines
read (1) or write (0) transmission) (the assigned I
2
C slave
address for the ISL6405 is 0001 00XX)
A sequence of data (1 byte + Acknowledge)
A stop condition (P)
System Register Format
R, W = Read and Write bit
R = Read-only bit
All bits reset to 0 at Power-On
SDA
SCL
FIGURE 3. ACKNOWLEDGE ON THE I
2
C BUS
1
2
8
9
ACKNOWLEDGE
FROM SLAVE
MSB
START
TABLE 2. INTERFACE PROTOCOL
S
0
0
0
1
0
0
0
R/W ACK
Data (8 bits)
ACK P
TABLE 3. SYSTEM REGISTER 1 (SR1)
R, W
R, W
R, W
R, W
R, W
R, W
R, W
R
SR1
DCL
ISEL1
ENT1
LLC1
VSEL1
EN1
OLF1
TABLE 4. SYSTEM REGISTER 2 (SR2)
R, W
R, W
R, W
R, W
R, W
R, W
R
R
SR2
ISEL2
ENT2
LLC2
VSEL2
EN2
OTF
OLF2
ISL6405
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