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6
Figure 3 shows the critical power components of the converter.
To minimize the voltage overshoot, the interconnecting wires
indicated by heavy lines should be part of a ground or power
plane in a printed circuit board. The components shown in
Figure 3 should be located as close together as possible.
Please note that the capacitors C
IN
and C
O
may each
represent numerous physical capacitors. Locate the
ISL6431A
within 3 inches of the MOSFETs, Q
1
and Q
2
. The circuit traces
for the MOSFETs’ gate and source connections from the
ISL6431A must be sized to handle up to 1A peak current.
Figure 4 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the COMP/OCSET pin and locate the
resistor, R
OSCET
close to the COMP/OCSET pin because
the internal current source is only 20
μ
A. Provide local V
CC
decoupling between VCC and GND pins. Locate the
capacitor, C
BOOT
as close as practical to the BOOT and
PHASE pins. All components used for feedback
compensation should be located as close to the IC a
practical.
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
error amplifier (Error Amp) output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a
pulse-width modulated (PWM) wave with an amplitude of
V
IN
at the PHASE node. The PWM wave is smoothed by the
output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6431A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 7. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
L
O
C
O
LGATE
UGATE
PHASE
Q
1
Q
2
V
IN
V
OUT
RETURN
ISL6431A
C
IN
L
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
+5V
ISL6431A
COMP/OCSET
GND
VCC
BOOT
D
1
L
O
C
O
V
OUT
L
Q
1
Q
2
PHASE
+V
IN
C
BOOT
C
VCC
R
O
+5V
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
2
C
1
COMP
V
OUT
FB
Z
FB
ISL6431A
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
-
Z
IN
OSC
FLC
2
π
x LO x CO
--------------------1
=
FESR
π
x ESR x CO
2
=
ISL6431A