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參數(shù)資料
| 型號： | ISL6523A |
| 廠商： | Intersil Corporation |
| 英文描述： | Adjustable Precision Shunt Regulator 3-SOT-89 0 to 70 |
| 中文描述： | VRM8.5雙雙PWM和線性電源系統(tǒng)控制器 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大小： | 408K |
| 代理商： | ISL6523A |
7
Soft-Start
The 1.8V supply designed to power the chipset (OUT4), cannot
lag the ATX 3.3V by more than 2V, at any time. To meet this
special requirement, the linear block controlling this output
operates independently of the chip’s power-on reset. Thus,
DRIVE4 is driven to raise the OUT4 voltage before the input
supplies reach their POR levels. As seen in Figure 5, at time T0
the power is turned on and the input supplies ramp up.
Immediately following, OUT4 is also ramped up, lagging the
ATX 3.3V by about 1.8V. At time T1, the POR function initiates
the SS24 soft-start sequence. Initially, the voltage on the SS24
pin rapidly increases to approximately 1V (this minimizes the
soft-start interval). Then, an internal 28
μ
A current source
charges an external capacitor (C
SS24
) on the SS24 pin to
about 4.5V. As the SS24 voltage increases, the PWM2 error
amplifier allows generation of PHASE pulses of increasing
width that charge the output capacitor(s), providing a smooth
transition to the final set voltage. The OUT4 reference (clamped
to SS24) increasing past the intermediary level, established
based on the ATX 3.3V presence at the VAUX pin, brings the
output in regulation soon after T2.
As OUT2 increases past the 90% power-good level, the second
soft-start (SS13) is released. Between T2 and T3, the SS13
pin voltage ramps from 0V to the valley of the oscillator’s
triangle wave (at 1.25V). Contingent upon OUT2 remaining
above 1.08V, the first PWM pulse on PHASE1 triggers the
VTTPG pin to go high. The oscillator’s triangular wave form
is compared to the clamped error amplifier output voltage.
As the SS13 pin voltage increases, the pulse-width on the
PHASE1 pin increases, bringing the OUT1 output within
regulation limits. Similarly, the SS13 voltage clamps the
reference voltage for OUT3, enabling a controlled output
voltage ramp-up. At time T4, all output voltages are within
power-good limits, situation reported by the PGOOD pin
going high.
The T2 to T3 time interval is dependent upon the value of
C
SS13
. The same capacitor is also responsible for the ramp-
up time of the OUT1 and OUT3 voltages. If selecting a
different capacitor then recommended in the circuit application
literature, consider the effects the different value will have on
the ramp-up time and inrush currents of the OUT1 and OUT3
outputs.
Fault Protection
All four outputs are monitored and protected against extreme
overload. The chip’s response to an output overload is
selective, depending on the faulting output.
An overvoltage on V
OUT1
output (VSEN1) disables outputs
1, 2, and 3, and latches the IC off. An under-voltage on
V
OUT4
output latches the IC off. A single overcurrent event
on outputs 1 or 2, or an under-voltage event on output 3,
increments the respective fault counter and triggers a
shutdown of outputs 1, 2, and 3, followed by a soft-start re-
start. After three consecutive fault events on either counter,
the chip is latched off. Removal of bias power resets both the
fault latch and the counters. Both counters are also reset by
a successful start-up of all the outputs.
Figure 6 shows a simplified schematic of the fault logic. The
overcurrent latches are set dependent upon the states of the
overcurrent (OC1 and OC2), output 3 under-voltage (UV3)
FIGURE 5. SOFT-START INTERVAL
0V
10V
0V
TIME
PGOOD
SS13
V
OUT2
(1.2V)
V
OUT4
(1.8V)
T1
T2
T4
T0
T5
3.0V
V
OUT1
(1.65V)
V
OUT3
(1.5V)
VTTPG
SS24
ATX 3.3V
ATX 5V
ATX 12V
T3
FAULT
LATCH
S
R
Q
POR
COUNTER
OC1
UV4
OC2
UV3
4V
SS13
FAULT
R
FIGURE 6. FAULT LOGIC - SIMPLIFIED SCHEMATIC
SS13UP
OC
LATCH
INHIBIT1,2,3
S
R
Q
OV
4V
0.8V
SS24
SS24UP
Q
SSDOWN
COUNTER
>
S
R
Q
OC
LATCH
R
>
ISL6523A
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