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參數(shù)資料
| 型號： | ISL6524EVAL1 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | VRM8.5 PWM and Triple Linear Power System Controller |
| 中文描述： | VRM8.5 PWM和三線性電源系統(tǒng)控制器 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 445K |
| 代理商： | ISL6524EVAL1 |
11
FN9015.3
April 18, 2005
Dedicate another solid layer as a power plane and break this
plane into smaller islands of common voltage levels. The
power plane should support the input power and output
power nodes. Use copper filled polygons on the top and
bottom circuit layers for the PHASE node, but do not
unnecessarily oversize this particular island. Since the
PHASE node is subject to very high dV/dt voltages, the stray
capacitor formed between these island and the surrounding
circuitry will tend to couple switching noise. Use the
remaining printed circuit layers for small signal wiring. The
wiring traces from the control IC to the MOSFET gate and
source should be sized to carry 2A peak currents.
PWM1 Controller Feedback Compensation
The PWM controller uses voltage-mode control for output
regulation. This section highlights the design consideration for a
voltage-mode controller requiring external compensation.
Figure 11 highlights the voltage-mode control loop for a
synchronous-rectified buck converter. The output voltage
(V
OUT
) is regulated to the Reference voltage level. The
reference voltage level is the DAC output voltage (DACOUT)
for the PWM. The error amplifier output (V
E/A
) is compared with
the oscillator (OSC) triangular wave to provide a pulse-width
modulated wave with an amplitude of V
IN
at the PHASE node.
The PWM wave is smoothed by the output filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain, given by V
IN
/V
OSC
, and shaped by the output filter, with
a double pole break frequency at F
LC
and a zero at F
ESR
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6524) and the impedance networks Z
IN
and
Z
FB
. The goal of the compensation network is to provide a
closed loop transfer function with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
o
.
The equations below relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 11. Use these guidelines for locating the poles
and zeros of the compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
)
3. Place 2
ND
Zero at Filter’s Double Pole
4. Place 1
ST
Pole at the ESR Zero
5. Place 2
ND
Pole at Half the Switching Frequency
6. Check Gain against Error Amplifier’s Open-Loop Gain
7. Estimate Phase Margin - Repeat if Necessary
FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND
ISLANDS
V
OUT1
Q1
Q2
Q3
Q4
C
SS24,13
+12V
C
VCC
VCC
VIA/THROUGH-HOLE CONNECTION TO GROUND PLANE
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
L
OUT
C
OUT1
CR1
ISL6524
C
IN
C
OUT2
V
OUT2
V
OUT3
+5V
IN
SS24
SS13
PGND
LGATE
UGATE
PHASE
DRIVE3
KEY
GND
DRIVE2
OCSET
R
OCSET
C
OCSET
L
V
OUT4
DRIVE4
+3.3V
IN
L
IN
Q5
C
OUT3
C
OUT4
L
L
L
+3.3V
IN
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
OSC
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
+
-
DRIVER
(PARASITIC)
Z
FB
+
-
DACOUT
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6524
Z
IN
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
Z
IN
F
LC
L
O
2
π
C
O
×
×
---------------------------------------
=
F
ESR
2
π
ESR
C
O
×
×
-----------------------------------------
=
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