參數(shù)資料
型號(hào)： ISL6526CR-T
廠商： INTERSIL CORP
元件分類： 穩(wěn)壓器
英文描述： Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
中文描述： 2 A SWITCHING CONTROLLER, 325 kHz SWITCHING FREQ-MAX, PQCC16
封裝： 5 X 5 MM, PLASTIC, MO-220-VHHB, QFN-16
文件頁(yè)數(shù)： 10/15頁(yè)
文件大?。?/td> 420K
代理商： ISL6526CR-T
10
width modulated (PWM) wave with an amplitude of V
IN
at
the PHASE node. The PWM wave is smoothed by the output
filter (L
O
and C
O
).
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6526) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 5. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick gain (R
2
/R
1
) for desired converter bandwidth.
2. Place first zero below filter’s double pole (~75% F
LC
).
3. Place second zero at filter’s double pole.
4. Place first pole at the ESR zero.
5. Place second pole at half the switching frequency.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin - repeat if necessary.
Compensation Break Frequency Equations
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 6 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
REFERENCE
L
O
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
DRIVER
(PARASITIC)
Z
FB
+
-
REFERENCE
R
1
R
3
R
2
C
3
C
1
C
2
COMP
V
OUT
FB
Z
FB
ISL6526
Z
IN
COMPARATOR
DRIVER
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
Z
IN
OSC
F
LC
2
π
x L
O
x C
O
-----------------------------------------
=
F
ESR
2
x ESR x C
O
------------------------------------------
=
F
Z2
1
R
3
)
x C
3
------------------------+
=
F
P1
2
π
x R
2
x
2
1
C
2
--------+
--------------------------------------------------------
=
F
P2
3
3
-----------------------------------
=
F
Z1
2
2
----------------------------------
=
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
F
LC
F
ESR
COMPENSATION
GAIN
G
FREQUENCY (Hz)
MODULATOR
GAIN
LOOP GAIN
20
-----------------
log
20
-------
log
ISL6526
相關(guān)PDF資料
PDF描述
ISL6526EVAL1 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
ISL6526EVAL2 Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
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