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參數(shù)資料
| 型號： | ISL6527IRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | SWITCHING CONTROLLER, 340 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 5 X 5 MM, ROHS COMPLIANT, PLASTIC, MO-220VHHB, QFN-16 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 403K |
| 代理商： | ISL6527IRZ-T |
12
FN9056.7
April 8, 2005
Some capacitor series available from reputable manufacturers
are surge current tested.
MOSFET Selection/Considerations
The ISL6527 requires two N-Channel power MOSFETs. These
should be selected based upon r
DS(ON)
, gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss components;
conduction loss and switching loss. The conduction losses are
the largest component of power dissipation for both the upper
and the lower MOSFETs. These losses are distributed between
the two MOSFETs according to duty factor. The switching
losses seen when sourcing current will be different from the
switching losses seen when sinking current. When sourcing
current, the upper MOSFET realizes most of the switching
losses. The lower switch realizes most of the switching losses
when the converter is sinking current (see the equations
below). These equations assume linear voltage-current
transitions and do not adequately model power loss due the
reverse-recovery of the upper and lower MOSFET’s body
diode. The gate-charge losses are dissipated by the ISL6527
and don't heat the MOSFETs. However, large gate-charge
increases the switching interval, t
SW
which increases the
MOSFET
switching losses. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate heatsink
may be necessary depending upon MOSFET power, package
type, ambient temperature and air flow.
Given the reduced available gate bias voltage (5V), logic-
level or sub-logic-level transistors should be used for both N-
MOSFETs. Caution should be exercised with devices
exhibiting very low V
GS(ON)
characteristics. The shoot-
through protection present aboard the ISL6527 may be
circumvented by these MOSFETs if they have large parasitic
impedances and/or capacitances that would inhibit the gate
of the MOSFET from being discharged below its threshold
level before the complementary MOSFET is turned on.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the upper
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 7. The
boot capacitor, C
BOOT
, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D
BOOT
conducts, to a voltage of CPVOUT less
the boot diode drop, V
D
, plus the voltage rise across
Q
LOWER
.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
upper MOSFET as shown:
where Q
GATE
is the maximum total gate charge of the upper
MOSFET, C
BOOT
is the bootstrap capacitance, V
BOOT1
is
the bootstrap voltage immediately before turn-on, and
V
BOOT2
is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the
gate drive begins to turn-off the upper MOSFET. A refresh
cycle ends when the upper MOSFET is turned on again,
which varies depending on the switching frequency and duty
cycle.
The minimum bootstrap capacitance can be calculated by
rearranging the previous equation and solving for CBOOT.
T
ypical gate charge values for MOSFETs considered in
these types of applications range from 20 to 100nC. Since
the voltage drop across Q
LOWER
is negligible, V
BOOT1
is
simply V
CPVOUT
- V
D
. A schottky diode is recommended to
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/ V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
s
is the switching frequency.
Losses while Sourcing current
Io
2
=
Losses while Sinking current
P
UPPER
= Io
2
x r
DS(ON)
x D
P
LOWER
Io
2
r
DS ON
)
×
1
D
–
(
)
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
=
P
UPPER
r
DS ON
)
×
D
×
1
2
--
Io
V
IN
×
t
SW
f
s
×
×
+
ISL6527
GND
LGATE
UGATE
PHASE
BOOT
VIN
NOTE:
V
G-S
≈
V
CC
-V
D
NOTE:
V
G-S
≈
V
CC
CBOOT
DBOOT
Q
UPPER
Q
LOWER
+
-
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
+
V
D
-
CPVOUT
Q
GATE
C
BOOT
V
BOOT1
V
BOOT2
–
(
)
×
=
C
BOOT
Q
BOOT1
V
BOOT2
------------------------–
≥
ISL6527
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