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參數(shù)資料
| 型號： | ISL6528 |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準電壓源/電流源 |
| 英文描述： | Dual Regulator - Standard Buck PWM and Linear Power Controller |
| 中文描述： | 雙穩(wěn)壓器-標準降壓PWM和線性功率控制器 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 390K |
| 代理商： | ISL6528 |
11
FN9038.3
December 28, 2004
load current when the base is fed with the minimum driver
output current.
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in a linear regulator is:
where I
O
is the maximum output current and V
OUT
is the
nominal output voltage of the linear regulator.
Diode Selection (D1)
Rectifier D1 conducts when MOSFET Q1 is off. The diode
should be a Schottky type for low power losses. The power
dissipation in the Schottky rectifier is approximated by:
where I
O
is the maximum output current of the PWM
converter, V
f
is the Schottky forward voltage drop, and D is
the duty cycle of the converter (defined as V
O
/V
IN
).
In addition to power dissipation, package selection and
heatsink requirements are the main design trade-offs in
choosing a Schottky rectifier. Since the three factors are
interrelated, the selection process is an iterative procedure.
The maximum junction temperature of the rectifier must
remain below the manufacturer’s specified value, typically
125°C. By using the package thermal resistance
specification and the Schottky power dissipation equation,
the junction temperature of the rectifier can be estimated. Be
sure to use the available airflow and ambient temperature to
determine the junction temperature rise.
Bootstrap Component Selection
External bootstrap components, a diode and capacitor, are
required to provide sufficient gate enhancement to the
MOSFET. The internal MOSFET gate driver is supplied by
the external bootstrap circuitry as shown in Figure 8. The
boot capacitor, C
BOOT
, develops a floating supply voltage
referenced to the PHASE pin. This supply is refreshed each
cycle, when D1 conducts, to a voltage of VCC less the boot
diode drop, V
D2
, plus the voltage rise across D1.
Just after the PWM switching cycle begins and the charge
transfer from the bootstrap capacitor to the gate capacitance
is complete, the voltage on the bootstrap capacitor is at its
lowest point during the switching cycle. The charge lost on
the bootstrap capacitor will be equal to the charge
transferred to the equivalent gate-source capacitance of the
MOSFET as shown in Equation 19.
where Q
GATE
is the maximum total gate charge of the
MOSFET, C
BOOT
is the bootstrap capacitance, V
BOOT1
is
the bootstrap voltage immediately before turn-on, and
V
BOOT2
is the bootstrap voltage immediately after turn-on.
The bootstrap capacitor begins its refresh cycle when the
gate drive begins to turn off the MOSFET. A refresh cycle
ends when the MOSFET is turned on again, which varies
depending on the switching frequency and duty cycle.
The minimum bootstrap capacitance can be calculated by
rearranging Equation 19 and solving for C
BOOT
.
Typical gate charge values for MOSFETs considered in
these types of applications range from 20–100nC. Since the
voltage drop across D2 is offset by the voltage drop across
D1, V
BOOT1
is simply VCC (+5V). A good rule is to keep the
voltage drop across the bootstrap capacitor no greater than
1V during the on-time of the MOSFET. Initial calculations
with V
BOOT2
no less than 4V will quickly help narrow the
bootstrap capacitor range.
For example, consider a MOSFET is chosen with a
maximum gate charge, Q
g
, of 100nC. Limiting the voltage
drop across the bootstrap capacitor to 1V results in a value
of no less than 0.1
μ
F. The tolerance of the ceramic capacitor
should also be considered when selecting the final bootstrap
capacitance value.
A fast recovery diode is recommended when selecting a
bootstrap diode to reduce the impact of reverse recovery
charge loss. Otherwise, the recovery charge, Q
RR
, would
have to be added to the gate charge of the MOSFET and
taken into consideration when calculating the minimum
bootstrap capacitance. Employing a Schottky diode over a
standard diode will also increase the gate drive voltage
available to enhance the MOSFET.
P
LINEAR
I
O
V
IN
V
OUT
–
(
)
×
(EQ. 17)
P
CONDUCTION
I
O
V
f
×
1
D
–
(
)
×
(EQ. 18)
Q
GATE
C
BOOT
V
BOOT1
V
BOOT2
–
(
)
×
=
(EQ. 19)
Q1
D1
C
BOOT
BOOT
UGATE
PHASE
VCC
+3.3V
+5V
D2
ISL6528
FIGURE 8. UPPER GATE DRIVE
C
BOOT
Q
BOOT1
V
BOOT2
V
≥
(EQ. 20)
ISL6528
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