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參數(shù)資料
| 型號： | ISL6529ACRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220VHHB, QFN-16 |
| 文件頁數(shù)： | 9/19頁 |
| 文件大小： | 623K |
| 代理商： | ISL6529ACRZ-T |
9
FN9070.5
April 12, 2005
However, since the value of R1 affects the values of the rest
of the compensation components, it is advisable to keep its
value less than 5k
. Depending on the value chosen for R1,
R4 can be calculated based on the following equation:
OUT1
–
If the output voltage desired is 0.8V, simply route VOUT1
back to the FB pin through R1, but do not populate R4.
The linear regulator output voltage is also set by means of
an external resistor divider as shown in Figure 5. The two
resistors used to set the output voltage should not exceed a
parallel equivalent value, referred to as R
FB
, of 5k
. This
restriction is due to the manner of implementation of the soft-
start function. The following relationship must be met:
R6
×
R6
+
To ensure the parallel combination of the feedback resistors
meets this criteria, choose a target value for R
FB
of less than
5k
and then apply the following equations:
where V
OUT2
is the desired linear regulator output voltage
and V
REF
is the internal reference voltage, 0.8V. For an
output voltage of 0.8V, simply populate R5 with a value less
than 5k
and do not populate R6.
Converter Shutdown
Pulling and holding the FB2 pin above a typical threshold of
1.28V will shut down both regulators. Upon release of the
FB2 pin, the regulators enter into a soft-start cycle which
brings both outputs back into regulation.
PWM Controller Feedback Compensation
A simplified representation of the voltage-mode control loop
used for output regulation by the converter is shown in
Figure 6. The output voltage, V
OUT
, is fed back to the
negative input of the error amplifier which is regulated to the
reference voltage level, V
REF
. The error amplifier output,
V
E/A
, is compared with the triangle wave produced by the
oscillator, V
OSC
, to provide a pulse-width modulated (PWM)
signal from the PWM comparator. This signal is then used to
switch the MOSFET and produce a PWM waveform with an
amplitude of V
IN
at the PHASE node. The square-wave
PHASE voltage is then smoothed by the output filter, L
OUT
and C
OUT
, to produce a DC voltage level.
The modulator transfer function is defined as V
OUT
/V
E/A
The internal PWM comparator and driver circuits equate to a
DC gain block dominated by the supply voltage, V
IN
, divided
by the peak-to-peak magnitude of the triangle wave,
V
OSC
.
The output filter components, L
OUT
and C
OUT
, shape the
overall modulator small-signal transfer function by
contributing a double pole break frequency at F
LC
and a
zero at F
ESR
.
FIGURE 4. OUTPUT VOLTAGE SELECTION OF THE PWM
+
R1
C3
C
OUT1
+5V
+3.3V
V
OUT1
R4
L
OUT
ISL6529
ISL6529A
Q1
FB
UGATE
12VCC
COMP
R2
C1
C2
R3
5VCC
+12V
Q2
LGATE
R4
R1
0.8V
0.8V
V
=
(EQ. 1)
R
FB
R5
5k
<
=
(EQ. 2)
DRIVE2
FB2
C
OUT2
ISL6529
ISL6529A
V
OUT2
+3.3V
IN
R5
R6
FIGURE 5. OUTPUT VOLTAGE SELECTION OF THE LINEAR
+
V
OUT2
0.8
1
R6
+
×
=
Q3
C4
R12
For frequency compensation considerations
set R5 to 4.64k and adjust R6 for the required voltage.
R5
V
REF
--V
R
FB
×
=
(EQ. 3)
R6
R5
V
REF
×
OUT2
V
=
(EQ. 4)
ISL6529, ISL6529A
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