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參數(shù)資料
| 型號： | ISL6529CRZ-T |
| 廠商： | INTERSIL CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Dual Regulator.Synchronous Rectified Buck PWM and Linear Power Controller |
| 中文描述： | SWITCHING CONTROLLER, 650 kHz SWITCHING FREQ-MAX, PQCC16 |
| 封裝： | 5 X 5 MM, LEAD FREE, PLASTIC, MO-220VHHB, QFN-16 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大?。?/td> | 623K |
| 代理商： | ISL6529CRZ-T |
10
FN9070.5
April 12, 2005
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
and the impedance networks Z
IN
and Z
FB
They provide the
link between the modulator transfer function and a
controllable closed loop transfer function of V
OUT
/V
REF
. The
goal of component selection for the compensation network is
to provide a loop gain with high 0dB crossing frequency
(f
0dB
) and adequate phase margin. Phase margin is the
difference between the closed loop phase at f
0dB
and 180
degrees .
Compensation Break Frequency Equations
Follow this procedure for selecting compensation
components by locating the poles and zeros of the
compensation network:
1. Set the loop gain (R2/R1) to provide a converter
bandwidth of one quarter of the switching frequency.
2. Place the first
compensation zero, F
Z1
, below the output
filter double pole (~75% F
LC
).
3. Position the second compensation zero, F
Z2
, at the
output filter double pole, F
LC
.
4. Locate the first compensation pole, F
P1
, at the output
filter ESR zero, F
ESR
.
5. Position the second compensation pole at half the
converter switching frequency, F
SW
.
6. Check gain against error amplifier’s open-loop gain.
7. Estimate phase margin; repeat if necessary.
FIGURE 6. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
V
OUT
V
REF
L
OUT
C
O
ESR
V
IN
V
OSC
ERROR
AMP
PWM
COMP
DRIVER
(PARASITIC)
+
-
0.8V
R1
R3
R2
C3
C2
C1
COMP
V
OUT
FB
Z
FB
ISL6529
Z
IN
DETAILED COMPENSATION COMPONENTS
PHASE
V
E/A
+
-
+
+
Z
FB
Z
IN
OSC
F
LC
L
O
2
π
C
O
×
×
-----------------1
=
F
ESR
π
ESR
C
O
×
×
2
=
(EQ. 5)
(EQ. 6)
F
Z1
π
R
×
2
C1
×
2
=
F
Z2
+
π
R1
R3
(
)
C3
×
×
2
=
F
P1
2
π
R
2
C2
C2
×
+
C1
×
×
--------------------------1
=
F
P2
π
R
×
3
C3
×
2
=
(EQ. 10)
(EQ. 11)
(EQ. 8)
(EQ. 9)
Zeros:
Poles:
X1
-
+
INTERNAL 0.8V
REFERENCE
C4
C
ISS
= C
GS
+ C
GD
REGULATED OUTPUT
R
LOAD
1/gfs
ESR
GATE
SOURCE
DRAIN
R
SAMPLE
C
OUTPUT
SIMPLIFIED MODEL
OF THE MOSFET
R12
AMPLIFIER
ERROR
ISL6529
DRIVE2
FB
C
GD
C
GS
C16
INPUT VOLTAGE
R5
R6
FIGURE 7. FIGURE A. SIMPLIFIED DIAGRAM OF THE LINEAR VOLTAGE REGULATOR
ISL6529, ISL6529A
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