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參數(shù)資料
| 型號(hào)： | ISL6536IB-T |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | Four Channel Supervisory IC |
| 中文描述： | 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8 |
| 封裝： | PLASTIC, MS-012-AA, SOIC-8 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 160K |
| 代理商： | ISL6536IB-T |
3
FN9114.2
December 28, 2004
Absolute Maximum Ratings
Thermal Information
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5.5V
VMON, PGOOD, ENABLE. . . . . . . . . . . . . . . . . -0.3V to VDD+0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4kV (HBM)
Operating Conditions
VDD Supply Voltage Range. . . . . . . . . . . . . . . . . . . . . +2.7V to +4V
Temperature Range (T
A
) . . . . . . . . . . . . . . . . . . . . . . .-40
°
C to 85
°
C
Thermal Resistance (Typical, Note 1)
8 LD SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150
°
C
Maximum Storage Temperature Range. . . . . . . . . . .-65
°
C to 150
°
C
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
°
C
θ
JA
(
°
C/W)
108
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1.
θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board. See Tech Brief TB379 for details.
2. 2. All voltages are relative to GND, unless otherwise specified.
Electrical Specifications
Nominal VDD = 3.3V, T
A
= T
J
= -40
°
C - 85
°
C, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
BIAS
IC Supply Current
I
VDD
VMON > VMON
_L2H
165
1000
μA
VDD Power On
VDD_L2H
VDD low to high
2.6
V
VDD Power On Reset
VDD_POR
VDD high to low
2.4
V
PGOOD
Pull-Down Current
PG
pd
VPGOOD = 0.5V
2
mA
Pull-Up Resistance
PG
pu
20
k
Output Low
V
PGl
VDD= 1V
0.05
0.1
V
Delay from VMON Rising
T
PG
delVMON
Last valid input = Vth to PG release
2
μs
Delay from EN Rising
T
PG
delENR
EN high to PG release
0.05
μs
Delay from EN Falling
T
PG
delENF
EN low to PG pulling low
0.015
μs
ENABLE
Rising Threshold
V
EN
ENABLE Low to High Threshold
0.4VDD
0.5VDD
0.6VDD
V
Threshold Hysteresis
V
EN_HYS
0.065
V
Pull-up Current
I
ENpu
VEN = 0.5V
10
μA
VMON Input
Falling Threshold
3.3VMON
_H2L
Tj=+25c
0.623
0.633
0.643
V
Falling Threshold Temp Coeff.
3.3VMON
_TC
100
uV/
°
C
Hysteresis
VVMON
_HYS
-
10
-
mV
Range
VMON
_RNG
-
8
-
mV
Glitch Filter Duration
TFIL
VMON glitch to PGOOD low Filter
-
30
-
μs
ISL6536
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