參數(shù)資料
型號(hào): ISL6536IBZ
廠商: INTERSIL CORP
元件分類: 電源管理
英文描述: PWM Control Circuit 16-SOIC -40 to 85
中文描述: 4-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
封裝: ROHS COMPLIANT, PLASTIC, MS-012AA, SOIC-8
文件頁數(shù): 4/6頁
文件大?。?/td> 160K
代理商: ISL6536IBZ
4
FN9114.2
December 28, 2004
ISL6536 Description and Operation
The ISL6536 is a four channel supervisory IC designed to
monitor multiple voltages greater than 0.7V. This IC is
suitable for both microprocessors or industrial system
applications.
Upon VDD bias power up the PGOOD output is held low with
VDD as low as 0V. Once biased to 2.6V and enabled the IC
continuously monitors from one to four voltages
independently through external resistor dividers comparing
each VMON pin voltage to an internal 0.63V reference.
Once all VMON input voltages rise above 0.63V the PGOOD
(power good) output signal is released and is pulled high via
an external pull resistor to indicate that the power conditions
have been met. The PGOOD output is an open-drain to
allow ORing of the signals and interfacing to a wide range of
logic levels.
Once any VMON input falls below 0.63V the PGOOD output
is pulled low, the VMON inputs are designed to reject fast
transients (30μs).
If less than four voltages are being monitored, connect the
unused VMON pins to VDD.
The PGOOD pin has an internal 20k
pull-up to VDD
making an external pull-up resistor unnecessary.
Figure 1 illustrates the operational timing diagram.
Typical Performance Curves
FIGURE 2. VDD CURRENT vs. VDD VOLTAGE
FIGURE 3. VMON THRESHOLD vs. VDD VOLTAGE
FIGURE 1. ISL6536 OPERATIONAL TIMING DIAGRAM
VTH
LAST EN/VMON INPUT
PGOOD OUTPUT
T
FIL
4/5 EN/VMON INPUTS HIGH
<T
FIL
0.5
0.4
0.3
0.2
0.1
0
VDD BIAS VOLTAGE (V)
0.6
V
2.6
3.0
3.33
3.66
4.0
VMON<VMON
_L2H
VMON>VMON
_L2H
0.645
0.642
0.639
0.636
0.633
0.627
V
VDD BIAS VOLTAGE (V)
3.3
2.6
3.9
0.630
3.7
3.5
ISL6536
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