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參數(shù)資料
| 型號(hào)： | ISL6545IRZ |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 穩(wěn)壓器 |
| 英文描述： | 5V or 12V Single Synchronous Buck Pulse-Width Modulation (PWM) Controller |
| 中文描述： | SWITCHING CONTROLLER, 330 kHz SWITCHING FREQ-MAX, PDSO10 |
| 封裝： | 3 X 3 MM, ROHS COMPLIANT, PLASTIC, MO-229WEED-3, DFN-10 |
| 文件頁(yè)數(shù)： | 6/16頁(yè) |
| 文件大小： | 302K |
| 代理商： | ISL6545IRZ |
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www.DataSheet4U.com
6
FN6305.3
November 15, 2006
Functional Description
Initialization (POR and OCP sampling)
Figure 1 shows a simplified timing diagram. The Power-On-
Reset (POR) function continually monitors the bias voltage at
the V
CC
pin. Once the rising POR threshold is exceeded
(V
POR
~4V nominal), the POR function initiates the
Overcurrent Protection (OCP) sample and hold operation
(while COMP/SD is ~1V). When the sampling is complete,
V
OUT
begins the soft-start ramp.
If the COMP/SD pin is held low during power-up, that will just
delay the initialization until it is released, and the COMP/SD
voltage is above the V
DISABLE
trip point.
Figure 2 shows a typical power-up sequence in more detail.
The initialization starts at T0, when either V
CC
rises above
V
POR
, or the COMP/SD pin is released (after POR). The
COMP/SD will be pulled up by an internal 20μA current
source, but the timing will not begin until the COMP/SD
exceeds the V
DISABLE
trip point (at T1). The external
capacitance of the disabling device, as well as the
compensation capacitors, will determine how quickly the
20μA current source will charge the COMP/SD pin. With
typical values, it should add a small delay compared to the
soft-start times. The COMP/SD will continue to ramp to ~1V.
From T1, there is a nominal 6.8ms delay, which allows the V
CC
pin to exceed 6.5V (if rising up towards 12V), so that the
internal bias regulator can turn on cleanly. At the same time, the
LGATE/OCSET pin is initialized, by disabling the LGATE driver
and drawing I
OCSET
(nominal 21.5
μ
A) through R
OCSET
. This
sets up a voltage that will represent the OCSET trip point. At
T2, there is a variable time period for the OCP sample and hold
operation (0 to 3.4ms nominal; the longer time occurs with the
higher overcurrent setting). The sample and hold uses a digital
counter and DAC to save the voltage, so the stored value does
not degrade, for as long as the V
CC
is above V
POR
. See the
Overcurrent Protection
on
page 7 for more details on the
equations and variables. Upon the completion of sample and
hold at T3, the soft-start operation is initiated, and the output
voltage ramps up between T4 and T5.
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on the
non-inverting terminal of the error amp from zero to 0.6V in a
nominal 6.8ms The output voltage will thus follow the ramp,
from zero to final value, in the same 6.8ms (the actual ramp
seen on the V
OUT
will be less than the nominal time, due to
some initialization timing, between T3 and T4).
The ramp is created digitally, so there will be 64 small discrete
steps. There is no simple way to change this ramp rate
externally, and it is the same for either frequency version of the
IC (300kHz or 600kHz).
After an initialization period (T3 to T4), the error amplifier
(COMP/SD pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.6V), the soft-
start is complete, and the output should be in regulation at the
expected voltage. This method provides a rapid and controlled
output voltage rise; there is no large inrush current charging the
output capacitors. The entire start-up sequence from POR
typically takes up to 17ms; up to 10.2ms for the delay and OCP
sample, and 6.8ms for the soft-start ramp.
Figure 3 shows the normal curve in blue; initialization begins
at T0, and the output ramps between T1 and T2. If the output
is pre-biased to a voltage less than the expected value, as
shown by the magenta curve, the ISL6545 will detect that
condition. Neither MOSFET will turn on until the soft-start
ramp voltage exceeds the output; V
OUT
starts seamlessly
ramping from there. If the output is pre-biased to a voltage
above the expected value, as in the red curve, neither
MOSFET will turn on until the end of the soft-start, at which
time it will pull the output voltage down to the final value. Any
GND>
COMP/SD (1V/DIV)
V
OUT
(1V/DIV)
V
CC
(2V/DIV)
~4V POR
FIGURE 1. POR AND SOFT-START OPERATION
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
0.4V
COMP/SD (0.25V/DIV)
LGATE/OCSET (0.25V/DIV)
LGATE
STARTS
SWITCHING
3.4ms
3.4ms
0 - 3.4ms
6.8ms
V
OUT
(0.5V/DIV)
GND>
T0 T1
T2
T3 T4
T5
ISL6545, ISL6545A
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