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參數(shù)資料
| 型號(hào)： | ISL6548A |
| 廠商： | Intersil Corporation |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | 500-mA Peak Step-Up, Step-Down, Inverting Switching Voltage Regulator 14-PDIP 0 to 70 |
| 中文描述： | ACPI的穩(wěn)壓器/雙通道DDR內(nèi)存控制器系統(tǒng) |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 494K |
| 代理商： | ISL6548A |
13
FN9189.1
July 22, 2005
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage
V
OSC
.
Modulator Break Frequency Equations
2
π
x
LO
x
CO
The compensation network consists of the error amplifier
(internal to the ISL6548A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 3. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 4 shows an asymptotic plot of the DC-DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 4 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Output Voltage Selection
The output voltage of the all the external voltage regulators
converter can be programmed to any level between their
individual input voltage and the internal reference, 0.8V. An
external resistor divider is used to scale the output voltage
relative to the reference voltage and feed it back to the
inverting input of the error amplifier, refer to the Typical
Application on page 4.
The output voltage programming resistor will depend on the
value chosen for the feedback resistor and the desired
output voltage of the particular regulator.
If the output voltage desired is 0.8V, simply route the output
voltage back to the respective FB pin through the feedback
resistor and do not populate the output voltage programming
resistor.
The output voltage for the internal V
TT_DDR
linear regulator
is set internal to the ISL6548A to track the V
DDQ
voltage by
50%. There is no need for external programming resistors.
FLC
------------------------------------------
=
FESR
ESR
x
CO
------ x
=
F
Z1
2
x R
2
x C
1
-----------------1
=
F
Z2
+
π
x R
1
R
3
)
x C
3
2
=
F
P1
2
π
x R
2
x
C
x C
2
1
+
C
2
C
---------------------------1
=
F
P2
π
x R
3
x C
3
2
=
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M
1M
100K
10K
1K
100
10
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
(R
2
/R
1
)
F
LC
F
ESR
COMPENSATION
GAIN
CLOSED LOOP
GAIN
G
FREQUENCY (Hz)
20LOG
(V
IN
/
V
OSC
)
MODULATOR
GAIN
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
R4
0.8V
0.8V
–
×
DDQ
V
=
R8
0.8V
–
×
GMCH
0.8V
V
=
R10
0.8V
×
TT_GMCH/CPU
0.8V
–
V
=
R12
DAC
0.8V
0.8V
–
×
V
=
ISL6548A
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| ISL6548A-6506EVAL1Z | 功能描述:EVALUATION BOARD ISL6548A-6506 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估板 - DC/DC 與 AC/DC（離線）SMPS 系列:- 產(chǎn)品培訓(xùn)模塊:Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:True Shutdown™ 主要目的:DC/DC，步升 輸出及類型:1，非隔離 功率 - 輸出:- 輸出電壓:- 電流 - 輸出:1A 輸入電壓:2.5 V ~ 5.5 V 穩(wěn)壓器拓?fù)浣Y(jié)構(gòu):升壓 頻率 - 開關(guān):3MHz 板類型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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| ISL6548CRZA | 功能描述:電壓模式 PWM 控制器 W/ANNEAL 4-IN-1G FOR DDR/I915/925 RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
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