參數(shù)資料
型號(hào): ISL6548ACRZ-T
廠商: INTERSIL CORP
元件分類: 穩(wěn)壓器
英文描述: ACPI Regulator/Controller for Dual Channel DDR Memory Systems
中文描述: DUAL SWITCHING CONTROLLER, 280 kHz SWITCHING FREQ-MAX, PQCC28
封裝: 6 X 6 MM, LEAD FREE, PLASTIC, MO-220-VJJC, MLPL, QFN-28
文件頁(yè)數(shù): 6/16頁(yè)
文件大?。?/td> 494K
代理商: ISL6548ACRZ-T
6
FN9189.1
July 22, 2005
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6548A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6548A enters a reduced
power mode and draws less than 1mA (I
CC_S5
) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1
μ
F capacitor.
P12V (Pin 3)
The V
TT
regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6548A provide the return path
for the V
TT
LDO, and switching MOSFET gate drivers. High
ground currents are conducted directly through the exposed
paddle of the QFN package which must be electrically
connected to the ground plane through a path as low in
inductance as possible.
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source
I
GATE
-
-0.8
-
A
UGATE and LGATE Sink
I
GATE
-
0.8
-
A
VTT REGULATOR
Upper Divider Impedance
R
U
-
2.5
-
k
Lower Divider Impedance
R
L
-
2.5
-
k
Maximum V
TT
Load Current
I
VTT_MAX
Periodic load applied with 30% duty cycle and
10ms period using ISL6548A_6506EVAL1
evaluation board (see Application Note AN1124)
-3
-
3
A
LINEAR REGULATORS
DC Gain
Guaranteed By Design
-
80
-
dB
Gain Bandwidth Product
GBWP
15
-
-
MHz
Slew Rate
SR
-
6
-
V/
μ
s
DRIVEn High Output Voltage
DRIVEn Unloaded
9.75
10.0
-
V
DRIVEn Low Output Voltage
-
0.16
0.50
V
DRIVEn High Output Source Current
V
FB
= 770mV, V
DRIVEn
= 0V
-
1.7
2.6
mA
DRIVEn Low Output Sink Current
V
FB
= 830mV, V
DRIVEn
= 10V
-
1.20
2.00
mA
VIDPGD
V
TT_GMCH/CPU
Rising Threshold
S0
.725
.740
-
V
V
TT_GMCH/CPU
Falling Threshold
S0
-
0.700
0.715
V
PROTECTION
OCSET Current Source
I
OCSET
18
20
22
μ
A
V
TT_DDR
Current Limit
By Design
-3.3
-
3.3
A
V
DDQ
OV Level
V
FB
/V
REF
S0/S3
-
115
-
%
V
DDQ
UV Level
V
FB
/V
REF
S0/S3
-
85
-
%
V
TT_DDR
OV Level
V
TT
/V
VREF_IN
S0
-
115
-
%
V
TT_DDR
UV Level
V
TT
/V
VREF_IN
S0
-
85
-
%
V
GMCH
UV Level
V
FB4
/V
REF
S0
-
85
-
%
V
TT_GMCH/CPU
UV Level
V
FB2
/V
REF
S0
-
85
-
%
Thermal Shutdown Limit
T
SD
By Design
-
140
-
°C
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ISL6548A
相關(guān)PDF資料
PDF描述
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ISL6548CRZA-T ACPI Regulator/Controller for Dual Channel DDR Memory Systems
ISL6548 ACPI Regulator/Controller for Dual Channel DDR Memory Systems
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